NEC 78K0S/K 1+ Series Application Note page 39

SET1 LVION
MOV A,
;----- 200 us wait
WAIT_200US:
DEC A
BNZ $WAIT_200US
;----- VDD >= VLVI wait processing
WAIT_LVI:
NOP
BT LVIF, $WAIT_LVI
SET1 LVIMD
generated when VDD < VLVI
;----- Set the clock <2>
SET_CLOCK:
MOV PPCC, #00000000B
(fxp) = fx (= 8 MHz)
= 8 MHz
;-----------------------------------------------------------------------------
; Initialize the port 0
;-----------------------------------------------------------------------------
MOV P0,
MOV PM0,
;-----------------------------------------------------------------------------
; Initialize the port 2
;-----------------------------------------------------------------------------
MOV P2,
high (turn off LED)
MOV PM2,
;-----------------------------------------------------------------------------
; Initialize the port 3
;-----------------------------------------------------------------------------
MOV P3,
MOV PM3,
;-----------------------------------------------------------------------------
; Initialize the port 4
;-----------------------------------------------------------------------------
MOV P4,
MOV PU4,
MOV PM4,
input mode
;-----------------------------------------------------------------------------
; Initialize the port 12
;-----------------------------------------------------------------------------
MOV P12,
MOV PM12, #11110000B
;-----------------------------------------------------------------------------
; Initialize the port 13
;-----------------------------------------------------------------------------
APPENDIX A PROGRAM LIST
; Enable the low-voltage detector operation
#40 ; Assign the 200 us wait count value
-----
; 0.5[us/clk] x 10[clk] x 40[count] = 200[us]
; Branch if VDD < VLVI
; Set so that an internal reset signal is
-----
; The clock supplied to the peripheral hardware
; -> The clock supplied to the CPU (fcpu) = fxp
#00000000B ; Set output latches of P00-P03 as low
#11110000B ; Set P00-P03 as output mode
#00000001B ; Set output latches of P21-P23 as low, P20 as
#11110000B ; Set P20-P23 as output mode
#00000000B ; Set output latches of P30-P33 as low
#11110000B ; Set P30-P33 as output mode
#00000000B ; Set output latches of P40-P47 as low
#00001000B ; Connect on-chip pull-up resistor to P43
#00001000B ; Set P40-P42 and P44-P47 as output mode, P43 as
#00000000B ; Set output latches of P120-P123 as low
; Set P120-P123 as output mode
Application Note U18887EJ1V0AN
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39