NEC 78K0S/K 1+ Series Application Note page 16

Cautions 1. The operation of the TM00 counter starts when values other than 0 and 0 (operation stop
mode) are set to TMC002 and TMC003, respectively. To stop the operation, set TMC002
and TMC003 to 0 and 0, respectively.
2. Write to the bits other than the OVF00 flag after stopping the timer operation.
3. When the timer is stopped, timer counts and timer interrupts do not occur, even if a signal
is input to the TI000/TI010 pin.
4. Except when the valid edge of the TI000 pin is selected as the count clock, stop the timer
operation before setting to the STOP mode or system clock stop mode; otherwise the
timer may malfunction when the system clock starts.
5. Set the valid edge of the TI000 pin with bits 4 and 5 of the PRM00 register after stopping
the timer operation.
6. If the clear & start mode is set upon a match between TM00 and CR000 or at the valid
edge of the TI000 pin, or the free-running mode is selected, when the set value of the
CR000 register is FFFFH and the TM00 counter value changes from FFFFH to 0000H, the
OVF00 flag is set to 1.
7. Even if the OVF00 flag is cleared before the next count clock is counted (before the TM00
counter becomes 0001H) after the TM00 counter overflows, it is re-set and clearing is
disabled.
8. Capture operation is performed at the fall of the count clock.
(INTTM0n0: n = 0, 1), however, occurs at the rise of the next count clock.
16
CHAPTER 4 SETTING METHODS
Application Note U18887EJ1V0AN
An interrupt request