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Super A3SEV-2C/4C-LN4 User's Manual
General Purpose I/O Header
The JGP1 (General Purpose Input/Output) header is a general purpose I/O expander on a
pin header via the SMBus. Each pin can be configured to be an input pin or output pin in
2.0mm pitch. The GPIO is controlled via the PCA9554APW 8-bit GPIO expansion from PCH
SMBus. The base address is 0xEFA0. The expander slave address is 0x70 for WRITE and
0x71 for READ. See the table below for pin definitions.
MH1
VGA
AUDIO FP
JPL4
JPL4:
1-2:ENABLE
2-3:DISABLE
JPAC1
JEDP1
JSMB1
U2
JSIM1
JMD2_SRW1
19
30
JMD1
JMD2
M.2-H PCI-E 3.0 X2/I-SATA0 M.2-P PCI-E 3.0 X1
USB2/3
19
1
USB4/5
BT1
JGP1
I-SATA1
2
LED2
JTPM1
JGP1 Header
Pin Definitions
Pin#
Definition
1
P3V3_DUAL
2
GND
3
JGP1_0
4
JGP1_4
5
JGP1_1
6
JGP1_5
7
JGP1_2
8
JGP1_6
9
JGP1_3
10
JGP1_7
USB0/1
USB6/7(3.1)
LAN3/4
LAN1/2
CPU
JBT1
JPME2
A3SEV-2C-LN4
JPME2:
1-2:NORMAL
2-3:ME MANUFACTURING MODE
BAR CODE
REV:1.00
DESIGNED IN USA
DIMMA1
DIMMB1
JSD1
SATA
DOM
POWER
JF1
PWR
NIC
NIC
HDD
PWR
RST
X OH/FF
ON
2
1
L
D E
L
D E
38
1. General Purpose Header
HDMI/DP
MH2
2
JITP1
59
BIOS LICENSE
2
JPV1
FAN1
MH4
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