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10.3 SSI Interface
10.3.1 Function Principle
If the clock is not interrupted for the time Tm-T/2 (output of further 25 periods), the shift register clocks once
again the same data value (error recognition in the evaluation). Some encoders contain a Power Failure Bit
(PFB). Attention: With the LIMAX2 the PFB is always "LOW"!
10.3.2 Data Protocol
23
22
21
20
19
18
PFB = Power Failure Bit
T = length of clock signal
Tm = monostable multivibrator time > 10µs
Figure 29: Data Protocol SSI Interface
10.3.3 Pin Assignment
Table 5: Pin Assignment SSI open cabel ends
Open cable ends
Color
White
Brown
Pink
Grey
Yellow
Green
Shield
Table 6: Pin Assignment SSI Interface
9-pin. D-SUB Connector
Pin
1
2
3
4
5
6
7
8
Housing
17
16
15
14
13
12
24 Data bits/3 Bytes
Function
0 V / GND
+ 24 VDC
Data -
Data +
CLK -
CLK +
PE
NEWLIFT FST1 (D9M0)
Function
DATA +
CLK -
-
24 VDC
0V / GND
DATA -
CLK +
-
PE
11
10
9
8
7
6
NEWLIFT FST2 (D9M1)
Function
0V / GND
CLK +
N.C.
DATA +
0V / GND
+ 24 VDC
CLK -
DATA -
N.C.
- 31 -
Connections and Interfaces
T
5
4
3
2
1
0
PFB
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