Analog Devices ADT7473 Manual page 11

ADT7473-1
ADDR SELECT
PWM3/ADDREN
CARE SHOULD BE TAKEN TO ENSURE THAT PIN 8
(PWM3/ADDREN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 8
FLOATING COULD CAUSE THE ADT7473-1 TO POWER UP WITH
AN UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7473-1 IS PLACED INTO ADDR SELECT
MODE, PINS 8 AND 4 CANNOT BE USED AS THE ALTERNATIVE
FUNCTIONS (PWM3, TACH4/THERM) UNLESS THE CORRECT
CIRCUIT IS MUXED IN AT THE CORRECT TIME OR DESIGNED TO
HANDLE THESE DUAL FUNCTIONS.
Figure 18. Unpredictable SMBus Address if Pin 8 is Unconnected
The ability to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices
sharing the same serial bus, for example, if more than one
ADT7473-1 is used in a system.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur during
the low period of the clock signal and remain stable during the
high period because a low-to-high transition when the clock is
high might be interpreted as a stop signal. The number of data
bytes that can be transmitted over the serial bus in a single read
or write operation is limited only by what the master and slave
devices can handle.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the tenth clock pulse to assert a stop condition. In
read mode, the master device overrides the acknowledge bit by
pulling the data line high during the low period before the
ninth clock pulse; this is known as No Acknowledge. The
master takes the data line low during the low period before the
tenth clock pulse, and then high during the tenth clock pulse to
assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
1
SCL
SDA 0
START BY
MASTER
Figure 19. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
V
CC
10kΩ
4
8
NC
DO NOT LEAVE ADDREN
UNCONNECTED! CAN
CAUSE UNPREDICTABLE
ADDRESSES.
1 0 1 1 1 0
FRAME 1
SERIAL BUS ADDRESS BYTE
SCL (CONTINUED)
SDA (CONTINUED)
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the ADT7473/ADT7473-1, write operations contain either
one or two bytes, and read operations contain one byte. To write
data to one of the device data registers or read data from it, the
address pointer register must be set so the correct data register
is addressed, and then data can be written into that register or
read from it. The first byte of a write operation always contains
an address that is stored in the address pointer register. If data is
written to the device, the write operation contains a second data
byte that is written to the register selected by the address
pointer register.
This write operation is shown in Figure 19. The device address
is sent over the bus, and then R/ W is set to 0. This is followed
by two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When reading data from a register, there are two possibilities:
•
If the ADT7473/ADT7473-1's address pointer register
value is unknown or not the desired value, it must first be
set to the correct value before data can be read from the
desired data register. This is done by performing a write to
the ADT7473/ADT7473-1, but only the data byte contain-
ing the register address is sent, because no data is written
to the register. This is shown in Figure 20.
A read operation is then performed consisting of the serial
bus address, R/ W bit set to 1, followed by the data byte
read from the data register. This is shown in Figure 21.
•
If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register, as shown in Figure 21.
9
1
D6
D7 D5
R/W
ACK. BY
ADT7473/ADT7473-1
ADDRESS POINTER REGISTER BYTE
1
D7 D6 D5 D4
FRAME 3
DATA BYTE
Rev. C | Page 11 of 72
ADT7473/ADT7473-1
D4 D3 D2 D1 D0
ACK. BY
ADT7473/ADT7473-1
FRAME 2
9
D2
D3 D1 D0
ACK. BY STOP BY
ADT7473/ADT7473-1 MASTER
9