Motorola ASTRO XTS 3000 Service Manual page 55

ODC is a clock that ABACUS provides to the ADSIC. Most internal
ADSIC functions are clocked by this ODC signal at a rate of 2.4 MHz;
it is available as soon as power is supplied to the circuitry. This signal
initially may be 2.4 or 4.8MHz after power-up. The ODC signal is
programmed by the ADSIC, via the SBI signal, to 2.4MHz when the
ADSIC is initialized by the MCU through the SPI bus. For any
functionality of the ADSIC to exist, including initial programming,
this reference clock must be present.
In the fundamental mode of operation, the ADSIC transfers raw IF data
to the DSP. The DSP can perform IF filtering and discriminator
functions on this data to obtain a baseband demodulated signal.
However, the ADSIC includes a digital IF and discriminator function,
and can provide this baseband demodulated signal directly to the DSP;
this is the typical mode of operation. The internal digital IF filter is
programmable up to 24 taps. These taps are programmed by the MCU
via the SPI interface.
The DSP accesses this data through its SSI serial port. This is a six-port,
synchronous serial bus. It is actually used by the DSP for both transmit
and receive data transfer, but only the receive functions will be
discussed here. The ADSIC transfers the data on the SRD line to the
DSP at a rate of 2.4 MHz. This is clocked synchronously by the ADSIC,
which provides a 2.4MHz clock on SC0. In addition, a 20kHz interrupt
is provided on SC1, signalling the arrival of a data packet. This means
that a new I and Q sample data packet is available to the DSP at a
20kHz rate, which represents the sampling rate of the received data.
The DSP then processes this data to extract audio, signalling, etc.,
based on the 20kHz interrupt.
In addition to the SPI programming bus, the ADSIC also contains a
parallel configuration bus consisting of D8-D23, A0-A2, A13-A15, RD*,
and WR*. This bus is used to access registers mapped into the DSP
memory starting at Y:FFF0. Some of these registers are used for
additional ADSIC configuration controlled directly by the DSP; some
of the registers are data registers for the speaker D/A. Analog speaker
audio is processed via this parallel bus, in which the DSP outputs the
speaker's audio digital data words to the speaker's D/A, and an analog
waveform, output on SDO (speaker data out), is generated. In
conjunction with the speaker D/A, the ADSIC contains a
programmable attenuator to set the rough signal attenuation.
However, the fine levels and differences among signal types are
adjusted through the DSP's software algorithms. The speaker D/A
attenuator setting is programmed by the MCU via the SPI bus.
The ADSIC provides an 8kHz interrupt to the DSP on IRQB for
processing the speaker data samples. IRQB is also one of the DSP mode
configuration pins at start-up. This 8kHz signal must be enabled
through the SPI programming bus by the MCU, and is necessary for
any audio processing to occur.
For secure messages, the analog signal data may be passed to the secure
module prior to processing speaker data for decryption. The DSP
transfers the data to and from the secure module through its SCI port,
consisting of TXD and RXD. The SCI port is a two-wire, duplex,
asynchronous serial port. Configuration and mode control of the
secure module is performed by the MCU via the SPI bus.
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