Tx Signal Path - Motorola ASTRO XTS 3000 Service Manual

TX Signal Path

IRQB
DSP56001
U405
SC0
SC1
SC2
SSI
SERIAL
SCK
SRD
STD
6-8
The ADSIC contains four general purpose I/O lines, labeled GCB0
through GCB3. These are connected to the AUDIO PA, and are used for
enabling the speaker and microphone amplifiers in the IC and for
steering the speaker and microphone audio paths from internal to
external. These I/O lines are controlled by the DSP through the ADSIC
parallel configuration bus. The DSP then writes speaker data samples,
at an 8kHz rate, to the speaker D/A register via the parallel bus, and
configures the AUDIO PA enable lines by writing the same bus to the
register controlling the I/O.
The audio PA provides about 20dB of gain and a dual-ended
differential output: SPKR_COMMON, and EXT_SPKR or INT_SPKR.
Internal or external speaker drive is achieved by changing the phase of
the outputs on INT_SPKR and EXT_SPKR to be either in-phase or out-
of-phase with SPKR_COMMON. The signal which is out-of-phase with
SPKR_COMMON will be driven.
Since all of the audio and signaling is processed in DSP software
algorithms, all types of audio and signaling follow this same path.
The transmit signal path follows some of the same design structure as
the receive signal path described above under "RX Signal Path" (refer
to Figure 6-10). It is advisable to read through the "RX Signal Path"
section prior to reading this section.
8KHz
D8-D23
A0-A2,A13-A15,RD*,WR*
2.4 MHz Receive Data Clock
20 KHz RX Data Interrupt
48KHz TX Data Interrupt
1.2 MHz Tx Data Serial Clock
Serial Receive Data
Serial Transmit Data
Figure 6-10 DSP RSSI Port - TX Mode
The ADSIC contains a microphone A/D with a programmable
attenuator for coarse level adjustment. As with the speaker D/A
attenuator, the microphone attenuator value is programmed by the
MCU via the SPI bus. The analog microphone signal from the audio PA
(U718) is input to the A/D on MAI (Mic Audio In). The microphone
A/D converts the analog signal to a series of data words and stores
them in internal registers. The DSP accesses this data through the
parallel data bus parallel configuration bus consisting of D8-D23, A0-
A2, A13-A15, RD*, and WR*. As with the speaker data samples, the DSP
reads the microphone samples from registers mapped into its memory
IRQB
MAI
ADSIC
GCB0-GCB3
U406
MODIN
VVO
SCKR
RFS
SBI
Data In
TFS
DIN
SCKT
Data In*
DIN-
RXD
ODC
TXD
IDC
To
Audio PA
U718
To VCO
SBI
To/From
ABACUS II
MAEPF-26002-O