Controller Memory Map - Motorola ASTRO XTS 3000 Service Manual

Controller Memory
Map
U1 is a binary-coded switch. The output pins from U1 are connected
to I/O ports on the controller, which provides a four-bit binary word
to the MCU, indicating which of the 16 positions the rotary is set to.
This switch provides an additional output, TG2, which is typically
used for coded or clear mode selection. It is an input to a control I/O
with a pull-up resistor. Selecting clear mode pulls this signal to logic
low.
Figure 6-15 depicts the controller section memory map for the parallel
data bus as used in normal modes of operation. There are three maps
available for normal operation, but map 2 is the only one used. In
bootstrap mode, the mapping is slightly different and will be
addressed later.
The external bus for the host controller (U701) consists of one 32k x 8
SRAM (U705), one 32k x 8 EEPROM (U706), one 1M x 8 FLASH ROM
(U727), and SLIC (U702) configuration registers. In addition, the DSP
host port is mapped into this bus through the SLIC address space. The
purpose of this bus is to interface the MCU (U701) to these devices.
The MCU executes program code stored in the FLASH ROM. On a
power-up reset, it fetches a vector from $FFFE, $FFFF in the ROM and
begins to execute code stored at this location. The external SRAM,
along with the internal 1k x 8 SRAM, is used for temporary variable
storage and stack space. The internal 512 bytes of EEPROM, along with
the external EEPROM, are used for non-volatile storage of customer-
specific information. More specifically, the internal EEPROM space
contains transceiver board tuning information and, on power-down,
some radio-state information is stored in the external EEPROM.
The SLIC is controlled through sixteen registers mapped into the MCU
memory at $1400-$14FF. This mapping is achieved by the following
signals from the MCU: R/W*, CSIO1*, HA0-HA4, HA8, and HA9. Upon
power-up, the MCU configures the SLIC including the memory map
by writing to these registers.
The SLIC memory management functions, in conjunction with the
chip selects provided by the MCU, provide the decoding logic for the
memory map that is dependent upon the "map" selected in the SLIC.
The MCU provides a chip select, CSGEN*, which decodes the valid
range for the external SRAM. In addition, CSI01* and CSPROG* are
provided to the SLIC decoding logic for the external EEPROM and
FLASH ROM respectively. The SLIC provides a chip select and banking
scheme for the EEPROM and FLASH ROM. The FLASH ROM is banked
into the map in 16kB blocks, with one 32kB common ROM block. The
external EEPROM may be swapped into one of the banked ROM areas.
This is all controlled by EE1CS*, ROM1CS*, ROM2CS*, HA14_OUT,
HA15_OUT, HA16, and HA17 from the SLIC (U702), and D0-D8 and
A0-A16 from the MCU (U701).
The SLIC provides three peripheral chip selects: XTSC1B, XTCS2B, and
XTCS3B. These can be configured to drive an external chip select when
its range of memory is addressed. XTSC1B is used to address the host
port interface to the DSP; XTSC2B is used to address a small portion of
external SRAM through gate U708; and XTSCB3 is used as general
purpose I/O for interrupting the secure module.
6-15