Receiver Back End - Motorola ASTRO XTS 3000 Service Manual

Receiver Back End

5-4
Since low-side injection is used, the LO frequency is offset below the
RF carrier by 73.35MHz, or Flo = Frf - 73.35MHz. The mixer utilizes
GaAs FETs in a double-balanced, Gilbert Cell configuration. The LO
port (pin 8) incorporates an internal buffer and a phase shift network
to eliminate the need for a LO transformer. The LO buffer bypass
capacitors (C208, C221, and C216) are connected to pin 10 of U205,
and should exhibit a nominal dc voltage of 1.2 to 1.4Vdc. Pin 11 of
U205 is LO buffer Vdd (5Vdc), with associated bypass capacitors C226
and C209 connected to the same node. An internal voltage divider
network within the LO buffer is bypassed to virtual ground at pin 12
of U205 through bypass capacitor C213. The mixer's LO port is
matched to the radio's PLL by a capacitive tap, C207 and C206.
A balun transformer (T202) is used to couple the RF signal into the
mixer. The primary winding of T202 is matched to the preceding stage
by capacitor C223, with C227 providing a dc block to ground. The
secondary winding of T202 provides a differential output, with a 180°
phase differential being achieved by setting the secondary center tap
to virtual ground using bypass capacitors C210, C211 and C212. The
secondary of transformer T202 is connected to pins 1 and 15 of the
mixer IC, which drives the source leg of dual FETs used to toggle the
paralleled differential amplifier configuration within the Gilbert Cell.
The final stage in the receiver front end is a two-pole crystal filter
(FL1). The crystal filter provides some of the receiver's adjacent
channel selectivity. The input to the crystal filter is matched to the 1st
mixer using components L605, C600, and C614. The output of the
crystal filter is matched to the input of IF buffer amplifier transistor
Q601 by components L600, C609, and C610.
The IF frequency on the collector of Q601 is applied to a second crystal
filter (FL2) through a matching circuit consisting of L601, L602, C604,
and C612. The filter supplies further attenuation at the IF sidebands to
increase the radio's selectivity. The output of FL2 is routed to pin 32 of
U401 through a matching circuit consisting of L603, C603, and C606,
and dc block capacitor C613.
In the ABACUS IC (U401), the first IF frequency is amplified and then
down-converted to 450kHz, the second IF frequency. At this point, the
analog signal is converted into two digital bit streams by a sigma-delta
A/D converter. The bit streams are then digitally filtered, mixed down
to baseband, and filtered again. The differential output data stream is
then sent to the ADSIC (U406) on the vocoder board, where it is
decoded to produce the recovered audio.
The ABACUS IC (U401) is electronically programmable, and the amount
of filtering, which is dependent on the radio channel spacing and signal
type, is controlled by the microcomputer. Additional filtering, which
used to be provided externally by a conventional ceramic filter, is
replaced by internal digital filters in the ABACUS IC. The ABACUS IC
contains a feedback AGC circuit to expand the dynamic range of the
sigma-delta converter. The differential output data contains the
quadrature (I and Q) information in 16-bit words, the AGC information
in a 9-bit word, imbedded word sync information, and fill bits,
dependent on sampling speed. A fractional-N synthesizer is also
incorporated on the ABACUS IC for 2nd LO generation.