Mcu System Clock; Dsp System Clock - Motorola ASTRO XTS 3000 Service Manual

MCU System Clock

DSP System Clock

6-18
banks from the ROM. This provides decoding for 128k bytes from the
ROM in the P: memory space. PS* is used to select A17 to provide an
additional 128k bytes of space in Dx: memory space for the ROM.
The ADSIC internal registers are decoded internally and start at $E000
in Dy:. These registers are decoded using A0-A2, A13-A15, and PS*
from the DSP. The ADSIC internal registers are 16 bits wide, so only
D8-D23 are used.
The DSP program code is stored in the FLASH ROM, U404. During
normal modes of operation, the DSP moves the appropriate program
code into the three SRAMs (U401, U402, and U403) and internal RAM
for execution. The DSP never executes program code from the FLASH
ROM itself. At power-up after reset, the DSP downloads 512 words
(1536 bytes) from the ROM, starting at $C000, and puts it into the
internal RAM, starting at $0000, where it is executed. This segment of
program code contains the interrupt vectors and the reset vector, and
is basically an expanded bootstrap code. When the MCU messages the
DSP that the ADSIC has been configured, the DSP overlays more code
from the ROM into external SRAM and begins to execute it. Overlays
occur at different times when the DSP moves code from the ROM into
external SRAM, depending on immediate mode of operation, such as
changing from transmit to receive.
The MCU (U701) system clock is provided by circuitry internal to the
MCU and is based on the crystal reference, Y100. The nominal
operating frequency is 7.3728MHz. This signal is available as a clock at
4XECLK on U701 and is provided to the SLIC (U702) for internal clock
timing. The MCU actually operates at a clock rate of 1/4 the crystal
reference frequency or 1.8432MHz. This clock is available at ECLK on
U701.
The MCU clock contains a crystal warp circuit comprised of L120,
Q102, and C162. This circuit is controlled by an I/O port (PA6) on the
MCU. This circuit moves the operating frequency of the oscillator
about 250ppM on certain receive channels to prevent interference
from the MCU bus noise.
The DSP (U405) system clock, DCLK, is provided by the ADSIC (U406).
It is based off the crystal reference, Y401, with a nominal operating
frequency of 33.0000 MHz. The ADSIC contains an internal clock-
divider circuit that can divide the system clock from 33MHz to
16.5MHz or 8.25MHz operation. The DSP controls this divider by
writing to the ADSIC parallel registers. The frequency is determined by
the processes the DSP is running and, to reduce system power
consumption, is generally configured to the slowest operating speed
possible.
The additional circuitry of CR402, L401, C416, C417, C419, and C422
make up a crystal warp circuit. This circuit is controlled by the OSCw
signal from ADSIC, which is configured by the host through the SPI
bus. The crystal warp circuit moves the operating frequency of the
oscillator about 400ppM on certain receive channels to prevent
interference from the DSP bus noise.