Adcx120Q1Evm-Pdk Hardware Settings; Figure 2-7. Pcmx120-Q1Evb Input Architecture - Texas Instruments ADCx120Q1EVM-PDK User Manual

Hardware Overview
the J3 header IOVDD. For 1.8-V operation, short pins 2 and 3 of header J3; for 3.3-V operation, short pins 1
and 2. When the motherboard is fully powered and the power supplies from the onboard LDOs are correct, the
green POWER LED (D3) turns ON. The USB READY LED indicates that a successful USB communication is
established between the AC-MB and the host computer.

2.2 ADCx120Q1EVM-PDK Hardware Settings

The PCMx120-Q1 evaluation module has several input configuration options and offers extensive flexibility to
allow the user to evaluate the device across multiple operation modes. The different operation modes are
highlighted in this section. The INxP and INxM pins of the PCMx120-Q1 can optionally connect to onboard
microphones for quick evaluation, and can be optionally configured to bypass the input decoupling capacitors
for evaluating the functionality of digital microphones, GPIOs, or in DC coupled applications.
diagram of the EVM input architecture.
6 ADCx120Q1EVM-PDK, PCMD3140Q1EVM-PDK Evaluation Module

Figure 2-7. PCMx120-Q1EVB Input Architecture

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SBAU398 – MARCH 2022
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