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ECP5 PCI Express Board User’s Guide Introduction The ECP5™ PCI Express Board allows designers to investigate and experiment with the features of the ECP5 Field-Programmable Gate Array. The features of the ECP5 PCI Express Board can assist engineers with rapid pro- totyping and testing of their specific designs.
ECP5 Device This board features an ECP5 FPGA in a 756-ball caBGA with a 1.1 V core supply. A complete description of this device can be found in DS1044, ECP5 Family Data Sheet.
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Expansion Card on CN1 Connector (Left) 0100 Expansion Card on CN2 Connector (Right) SW7 includes the ECP5 CFG pins (1=Up, 0=Down) which allow the configuration mode of the ECP5 to be selected. Switches are the right side of SW7 where SW7[1]=CFG0, SW7[2]=CFG1, SW7[3]=CFG2...
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A Micron N25Q128A device is populated on-board. The Serial SPI Flash memory device can be configured easily via the ECP5 JTAG port. This mode enables the FPGA to be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device.
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5. Click OK in the Device Properties dialog box. You will return to the main configuration screen. 6. Using SW6 set the ECP5 CFG pins to 010. 7. From the main programming window, select Go from the top toolbar. This begins the SPI Serial Flash program-...
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(See Appendix B, "Clock Generation" and "LPDDR3" sheets) The ECP5 PCI Express Board allows for several clock source options. Some of these options are controlled via the ispClock5304 programmable clock manager device. The clock manager will be supplied by a 54 MHz clock on- board oscillator or an external clock source.
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ECP5 PCI Express Board User’s Guide FPGA Test Pins (See Appendix B, "ECP5 Config" and "LEDs and Switches" sheets) General Purpose DIP Switches General purpose FPGA pins are available for user applications. FPGA pins are connected to switch SW4, SW7 with a piano style DIP switch.
LPDDR3 Memory Device (See Appendix B, "LPDDR" sheet) • The ECP5 PCI Express Board is equipped with a LPDDR3 memory device (1.2 V, 64 Mb/x32, 96-ball FBGA, 1600 MHz) such as the Micron EDF8132A1MC device. • The LPDDR3 memory is limited to a 16-bit wide memory controller interface.
Table 6. PHY Status Indicators Status Description RJ45 (Yellow) LED RX RJ45 (Yellow) LED TX The Marvell 88E1512 device communicates via a RGMII interface to the ECP5 device. Table 7. FPGA GPIO to RGMII Interfaces Signal RxClk RxCtrl AC28 RxD0...
TP22, TP24 PMOD (See Appendix B, "ECP5 Config" sheet) The ECP5 connects to a PMOD connector J3. To isolate the PVMOD connector from the FTDI device set all SW5 switches to 1 (Up=1). Figure 10. PMOD Connector and Switches Expansion Headers/Connectors (See Appendix B, "Card #1"...
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