Table of Contents
Advertisement
Configuring the HP Processor Probe for PowerPC 603/603e
Processor Memory Cache Configuration Items
Configuring data memory write operations
Although the PowerPC processor has one contiguous physical memory
address space that can hold both data and instructions, it has separate
caches for instructions and data. These separate caches must be considered
in order to keep the caches and memory coherent during memory write
operations. These settings are only used for memory write operations. Code
download always writes to physical memory and disables any cache entries
containing addresses written for improved performance. Some host
interfaces use the code download mode for all memory write operations so
this setting may or may not have any effect on your debugger.
Only the memory write command allows specifying instruction or data
memory operations. This may not be provided by your debugger interface. If
not specified, memory write operations are always instruction memory.
If the data cache is disabled, a data memory write will always write to
physical memory and this configuration setting is ignored.
cf dmwrop=mm
A data writes to addresses that are valid in the data cache will write the value
only to the cache and mark the cache line modified as "dirty" which will
indicate to the cpu that the cache line must be written to memory. A data
write that is not valid in the data cache will only be written to physical
memory.
cf dmwrop=thru
A data memory write to an address that is valid in the data cache will write to
both cache and physical memory. If the address is not valid in the cache,
only physical memory will be modified.
cf dmwrop=bypass
A data memory write will only be written to physical memory ignoring the
cache.
N o t e
The cf dmwrop=bypass setting should be used with extreme caution
because dirty cache entries may be written by the processor over the new
data value written to memory by the HP processor probe.
Default: cf dmwrop=mm
51
Advertisement
Table of Contents
