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Configuring the HP Processor Probe for PowerPC 603/603e
Processor Memory Cache Configuration Items
Configuring instruction memory write operations
Although the PowerPC processor have one contiguous physical memory
address space that can hold both data and instructions, it has separate
caches for instructions and data. These separate caches must be considered
in order to keep the caches and memory coherent during memory write
operations. Code download always writes to physical memory and disables
any cache entries containing addresses written for improved performance.
Some host interfaces use the code download mode for all memory write
operations so this setting may or may not have any effect on your debugger.
Only the memory write command allows specifying instruction or data
memory operations. Access to this may not be provided by your debugger
interface. If not specified, memory write operations are always instruction
memory.
If the instruction and data caches are both disabled, an instruction memory
write will always write to physical memory and this configuration setting is
ignored. If the instruction cache is disabled, instruction memory writes will
always write to physical memory and the data cache will be either updated or
bypassed depending on this configuration setting.
This configuration setting controls the behavior of both caches when doing
instruction memory writes so that instruction memory writes can be used for
all memory operations if desired.
cf imwrop=upd_dcb
This stands for instruction cache update, data cache bypass. An instruction
memory write to an address that is valid in the instruction cache will write
the value to both the instruction cache and memory. The data cache will be
bypassed even if the address is valid in the data cache.
cf imwrop=upd_dcu
This stands for update instruction cache and update data cache. An
instruction memory write to an address that is valid in both caches will write
the value to both caches and physical memory.
cf imwrop=inv_dcb
This stands for instruction cache invalidate and data cache bypass. An
instruction memory write will invalidate the instruction cache if valid and
write only to physical memory. The data cache is not modified even if valid.
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