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Configuring the HP Processor Probe for PowerPC 603/603e
General Configuration Items
Generating parity bits on memory operations
The PowerPC processor generates parity bits on both address and data lines
when running user code. When used in debug mode these bits must be
generated separately slowing down memory operations. Since memory
operations on the PowerPC are slow as it is and many target systems do not
check parity, parity is only generated if requested.
cf parity=off
Do not generate the parity bits for memory operations from the processor
probe. This provides better performance, but will not work correctly when
accessing devices that check the parity bits.
cf parity=on
Generate the parity bits for memory operations. Currently, only parity bits
for the memory data lines are generated. Parity bits on the address lines are
not. This may change in future firmware versions.
Default: cf parity=off
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