Xilinx Virtex-II Development Kit ................................................................................................................................................................. 1
Table of Contents ............................................................................................................................................................................................. 2
Figures ................................................................................................................................................................................................................ 3
Tables.................................................................................................................................................................................................................. 3
1.0
Introduction..................................................................................................................................................................................... 4
1.1
Description.................................................................................................................................................................................. 4
1.2
Features:....................................................................................................................................................................................... 4
1.3
Demo Applications:................................................................................................................................................................... 4
1.4
Ordering Information: .............................................................................................................................................................. 5
2.0
User Information............................................................................................................................................................................ 5
2.1
Power ........................................................................................................................................................................................... 5
2.2
Configuration.............................................................................................................................................................................. 5
2.2.1
Boundary scan Configuration.............................................................................................................................................. 6
2.2.2
System ACE MPM Configuration...................................................................................................................................... 6
2.2.3
2.2.4
Configuration Modes............................................................................................................................................................ 7
2.2.5
JTAG Chain ........................................................................................................................................................................... 8
2.3
Jumper Settings........................................................................................................................................................................... 9
3.0
Hardware........................................................................................................................................................................................ 11
3.1
Virtex-II FPGA........................................................................................................................................................................ 12
3.1.1
LVDS..................................................................................................................................................................................... 12
3.2
Memory...................................................................................................................................................................................... 12
3.2.1
DDR SDRAM ..................................................................................................................................................................... 12
3.2.2
Flash....................................................................................................................................................................................... 12
3.3
Communication........................................................................................................................................................................ 12
3.3.1
RS232 Transceiver............................................................................................................................................................... 12
3.4
LED ........................................................................................................................................................................................... 13
3.5
Dip Switches ............................................................................................................................................................................. 13
3.6
Connectors ................................................................................................................................................................................ 13
3.6.1
General I/O Interface ........................................................................................................................................................ 14
3.6.1.1
LVDS ........................................................................................................................................................................... 16
3.6.2
3.6.3
3.6.4
Miscellaneous Connectors ................................................................................................................................................. 20
3.7
PCI/PCIX................................................................................................................................................................................. 21
3.8
Evaluation Boards.................................................................................................................................................................... 23
3.9
Extender Card Board .............................................................................................................................................................. 23
3.10
Power ......................................................................................................................................................................................... 23
3.10.1
FPGA I/O Voltage (Vcco) ........................................................................................................................................... 23
3.10.2
FPGA Reference Voltage (Vref) .................................................................................................................................. 23
3.11
Configuration Modes............................................................................................................................................................... 23
4.0
Test Designs .................................................................................................................................................................................. 24
4.1
On-board Flash Test ............................................................................................................................................................... 25
4.2
PCI/PCI-X Test....................................................................................................................................................................... 25
4.3
Switch/LED Test .................................................................................................................................................................... 25
4.4
Avbus Connector Test ............................................................................................................................................................ 25
4.5
DDR SDRAM Test ................................................................................................................................................................. 25
5.0
Example VHDL Project.............................................................................................................................................................. 25
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Avnet Design Services
Released
Table of Contents
2 of 25
Rev 1.0
06/08/2004
Literature # ADS-xxxx04
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