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Chapter 2: Probing Considerations
Resistive Loading Effects
Conclusion
In conclusion we can review the issues by using the effect the 54701A Active
Probe (100 kΩ, 0.6 pF) has while measuring a fast CMOS gate.
Resistive Loading
Resistive loading is caused by the input resistance of the probe. When the
CMOS output is high (5 V) the 100 kΩ input resistance of the probe draws 50
mA. A CMOS gate can drive many times this current, so the load is
insignificant. In addition, the output impedance of a CMOS gate is the on
resistance of the output FET. Whether high or low, this is typically less than
100 Ω. The voltage divider of 100 Ω and 100 kΩ is also insignificant and will
not change the value of either state of the gate.
Capacitive Loading
CMOS gates typically have an input capacitance between 5 and 10 pF. The
traces between gates will contribute another 5 to 10 pF, which gives a total of
10 to 20 pF. The 0.6-pF input capacitance of the 54701A probe is about 3% to
6% that of the circuit capacitance. It will not significantly change the time
constant in the node being probed.
Ground Inductance
The CMOS gate has a risetime approaching 1 ns. This equates to a bandwidth
of 350 MHz (equation 4). If we use the walking-stick ground (about 20 nH)
provided with the 54701A probe, the probe resonance will be about 1.45 GHz
(equation 3). We can see that the CMOS equivalent bandwidth (350 MHz) is
at less than half the resonant frequency of the probe. This fits within the rule
of thumb given previously, that to avoid ringing in the response, the resonance
of the probe should be at least twice the frequency of the energy in the signal.
Bandwidth
Although it was specifically not covered in this chapter, the bandwidth of the
probe and oscilloscope combination is also very important. As previously
noted, with CMOS signals of 1 ns risetimes the signal bandwidth is 350 MHz.
This means for an accurate representation the probe and oscilloscope
combination should have at least a 3-to-1 margin in bandwidth, at least
1.05GHz.
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