Panasonic KX-HCM110A Service Manual page 52

Registry settings are performed in I2C<SCK, SDA> (IC2:22/23 pin) by the CPU (IC103) on the CPU board.
CMOS Color Image Sensor (IC2)
CMOS Color Image Sensor (IC2)
Operating voltage: +2.8V
- E+2.8VA: Analog block voltage
- E+2.8VD: Digital block voltage
Package:40pin CLCC
Image sensor and image-processing circuit embedded
Total pixels: 652 ~492 pixels
Effective pixels: 652~488 pixels
Image area: 1/4inch optical format
Color filter: RGB Bayer format
Input clock: 25MHz (To be supplied through the oscillation circuit in IC1 and X1.)
13.3. JPEG BLOCK
- The IC103 is a system LSI for a network camera containing the CPU.
- The JPEC Encode Circuit, the Memory Management Unit(MMU) and the
SDRAM Controller are built into this LSI.
- The image data(YUV) inputted from a Camera Block is captured to the
SDRAM through the JPEG Encode Block, the MMC and the SDRAM
Controller. (1)
- The captured YUV data are inputted to the JPEG Encode Block again
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