Tektronix Socket 7 TMS109A Instruction Manual
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Tektronix Socket 7 TMS109A Instruction Manual

Tektronix Socket 7 TMS109A Instruction Manual

Microprocessor support
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Instruction Manual
TMS 109A
Socket 7 Microprocessor Support
071-0497-01
Warning
The servicing instructions are for use by
qualified personnel only. To avoid personal
injury, do not perform any servicing unless you
are qualified to do so. Refer to all safety
summaries prior to performing service.

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Summary of Contents for Tektronix Socket 7 TMS109A

  • Page 1 Instruction Manual TMS 109A Socket 7 Microprocessor Support 071-0497-01 Warning The servicing instructions are for use by qualified personnel only. To avoid personal injury, do not perform any servicing unless you are qualified to do so. Refer to all safety summaries prior to performing service.
  • Page 2 Copyright Tektronix, Inc. All rights reserved. Licensed software products are owned by Tektronix or its suppliers and are protected by United States copyright laws and international treaty provisions. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013, or subparagraphs (c)(1) and (2) of the...
  • Page 3 In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration of the warranty period. If Tektronix is unable to provide a replacement that is free from defects in materials and workmanship within a reasonable time thereafter, Customer may terminate the license for this software product and return this software product and any associated materials for credit or refund.
  • Page 4 Tektronix, with shipping charges prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a location within the country in which the Tektronix service center is located. Customer shall be responsible for paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations.

  • Page 5: Table Of Contents

    ..........Contacting Tektronix .
  • Page 6 Table of Contents Software Display Format ........2–15 Control Flow Display Format .
  • Page 7 Table of Contents List of Figures Figure 1–1: Jumper locations on the probe adapter ....1–5 Figure 1–2: Connecting a probe to the probe adapter ... . . 1–7 Figure 1–3: Protective sockets .
  • Page 8 Table of Contents List of Tables Table 1–1: Jumper positions and function ..... . 1–4 Table 1–2: ITP (J580) signal Information .

  • Page 9: General Safety Summary

    General Safety Summary Review the following safety precautions to avoid injury and prevent damage to this product or any products connected to it. To avoid potential hazards, use this product only as specified. Only qualified personnel should perform service procedures. While using this product, you may need to access other parts of the system.
  • Page 10 General Safety Summary Do Not Operate in an Explosive Atmosphere. Keep Product Surfaces Clean and Dry. Provide Proper Ventilation. Refer to the manual’s installation instructions for details on installing the product so it has proper ventilation. Symbols and Terms Terms in this Manual. These terms may appear in this manual: WARNING.

  • Page 11: Service Safety Summary

    Service Safety Summary Only qualified personnel should perform service procedures. Read this Service Safety Summary and the General Safety Summary before performing any service procedures. Do Not Service Alone. Do not perform internal service or adjustments of this product unless another person capable of rendering first aid and resuscitation is present.
  • Page 12 Service Safety Summary viii TMS 109A Socket 7 Microprocessor Support...

  • Page 13: Preface

    This instruction manual contains specific information about the TMS 109A Sock- et 7 microprocessor support package and is part of a set of information on how to operate this product on compatible Tektronix logic analyzers. If you are familiar with operating microprocessor support packages on the logic analyzer for which the TMS 109A Socket 7 support was purchased, you will only need this instruction manual to set up and run the support.

  • Page 14: Contacting Tektronix

    Preface Contacting Tektronix Product For questions about using Tektronix measurement products, call Support toll free in North America: 1-800-TEK-WIDE (1-800-835-9433 ext. 2400) 6:00 a.m. – 5:00 p.m. Pacific time Or contact us by e-mail: tm_app_supp@tek.com For product support outside of North America, contact your local Tektronix distributor or sales office.

  • Page 15: Getting Started

    Getting Started...

  • Page 17: Support Package Description

    The label on the microprocessor support floppy disk states which version of logic analyzer software the support is compatible with. Logic Analyzer Configuration To use the TMS 109A Socket 7 support package, the Tektronix logic analyzer must be equipped with a 136-channel module at a minimum. TMS 109A Socket 7 Microprocessor Support...

  • Page 18: Requirements And Restrictions

    Socket 7 microprocessors at bus speeds of up to 100 MHz; the tested clock speed is 100 MHz. This specification is valid at the time this manual was printed. Contact your Tektronix sales representative for current information on the fastest devices supported.

  • Page 19: Functionality Not Supported

    Getting Started Probe Mode Cycles. Probe Mode cycles are not identified. Directory Table and Descriptor Table Reads and Writes. These reads and writes are not disassembled. Bus Anomalies. Some combinations of instructions and operating modes of the microprocessor can cause additional cycles to be fetched. This behavior is unpredictable, not documented, and can cause the disassembler to operate incorrectly with fetched cycles.

  • Page 20: Configuring The Probe Adapter

    Getting Started Configuring the Probe Adapter There are five jumpers on the probe adapter. Table 1–1 lists the jumper positions and functions. Table 1–1: Jumper positions and function Probe adapter Position Function J240 1–2 When the processor extends the clock speed to below 40 MHz, the jumpered pins 1-2 MFG_TEST turn the phased lock loop into a buffer that disables the phased lock loop signal.

  • Page 21: Mfg_Test Jumper

    Getting Started CLK Jumper The CLK jumper (J250 on the probe adapter) should be placed in the 40–150 MHz position to acquire data from a system running at or faster than 45 MHz. The jumper should be placed in the 20–75 MHz position to acquire data from a system running slower than 45 MHz.

  • Page 22: Tracking Jumper

    Getting Started When the jumper is open (not connected), the Socket 7 support acquires the D/P# signal from an external source, and you will have to route the D/P# signal to pin 1 of this jumper externally. This allows you to probe your system from the dual socket as long as the D/P# signal is accessible on the system under test.

  • Page 23: Remove The Microprocessor

    Getting Started 2. To discharge your stored static electricity, touch the ground connector located on the back of the logic analyzer. Then, touch any of the ground pins of the probe adapter to discharge stored static electricity from the probe adapter. 3.

  • Page 24: Choose A Protective Socket

    Getting Started Choose a Protective 7. Choose the correct protective socket. Socket Choose the 321-pin or 296-pin protective socket depending on the processor pinout (see Figure 1–3). NOTE. Use one protective socket at a time. Do not install a protective socket without removing all existing sockets from the system under test and from the bottom of the probe adapter assembly.

  • Page 25: Insert Probe Adapter

    Getting Started Insert Probe Adapter 11. Insert the probe adapter into the installed protective socket as shown in Figure 1–4. Pin A3 Pin A3 Protective socket System under test Figure 1–4: Placing the socket and probe adapter onto the system under test TMS 109A Socket 7 Microprocessor Support 1–9...

  • Page 26: Insert Microprocessor In The Probe Adapter

    Getting Started CAUTION. To prevent permanent damage to the microprocessor once power is applied, correctly place the microprocessor into the probe adapter. Insert Microprocessor in 12. Insert the microprocessor into the probe adapter as shown in Figure 1–5. the Probe Adapter Microprocessor Pin A3 System under test...

  • Page 27: Table 1-2: Itp (J580) Signal Information

    Getting Started NOTE. The ITP connection is implemented as a point-to-point connection. As such, it cannot be used in a loopthrough mode for programming other Socket 7 modules. Table 1–2 lists the pin-to-signal assignments of the In-Target Probe (ITP) connector J580 on the probe adapter. Table 1–2: ITP (J580) signal Information Pin number Signal name...

  • Page 28: Figure 1-6: Itp And System Reset Pin Locations On The Probe Adapter

    Getting Started J260, ITP reset signal J580, ITP connector Figure 1–6: ITP and system reset pin locations on the probe adapter Optional System Reset. The ITP circuitry on the Interposer board does not allow external ITP debugging hardware to induce a system reset through the DBRESET# signal on the ITP connector.

  • Page 29: Applying And Removing Power

    CAUTION. To prevent possible permanent damage to the probe adapter and Socket 7 microprocessor., use the +5 V power supply provided by Tektronix. Do not mistake another power supply that looks similar for the +5 V power supply. 1. Connect the +5 V power supply to the jack on the probe adapter. Figure 1–7 shows the location of the jack on the probe adapter.

  • Page 30: Channel Assignments

    Getting Started Power jack Figure 1–7: Power jack location on the probe adapter Channel Assignments Channel assignments shown in Tables 1–4 through 1–10 use the following conventions: A pound sign (#) following a signal name indicates an active low signal. All signals are required by the support unless indicated otherwise.
  • Page 31 Getting Started Table 1–4: Address channel group assignments (Cont.) Socket 7 order signal name Section:channel A3:3 A3:2 A3:1 A3:0 A2:7 A2:6 A2:5 A2:4 A2:3 A2:2 A2:1 A2:0 A1:7 A1:6 A1:5 A1:4 A1:3 A1:2 A1:1 A1:0 A0:7 A0:6 A0:5 A0:4 A0:3 A0:2 A2_D A0:1...

  • Page 32: Table 1-5: Data Channel Group Assignments

    Getting Started Table 1–5: Data channel group assignments Socket 7 order signal name Section:channel E3:7 E3:6 E3:5 E3:4 E3:3 E3:2 E3:1 E3:0 E2:7 E2:6 E2:5 E2:4 E2:3 E2:2 E2:1 E2:0 E1:7 E1:6 E1:5 E1:4 E1:3 E1:2 E1:1 E1:0 E0:7 E0:6 E0:5 E0:4 E0:3...

  • Page 33: Table 1-6: Data_Lo Channel Group Assignments

    Getting Started Table 1–6 lists the probe section and channel assignments for the Data_Lo group and the microprocessor signal for each channel connect. By default the Data_Lo channel group assignments are displayed in hexadecimal. Table 1–6: Data_Lo channel group assignments Socket 7 order signal name...

  • Page 34: Table 1-7: Control Channel Group Assignments

    Getting Started Table 1–6: Data_Lo channel group assignments (Cont.) Socket 7 order signal name Section:channel D0:2 D0:1 D0:0 Table 1–7 lists the probe section and channel assignments for the Control group and the microprocessor signal for each channel connect. The symbol table file name is Ctrl.

  • Page 35: Table 1-8: Data Size Channel Group Assignments

    Getting Started Table 1–8 lists the probe section and channel assignments for the Data Size group and the microprocessor signal for each channel connect. By default the Data Size channel group assignments are not displayed. Table 1–8: Data Size channel group assignments Socket 7 order Section:channel...

  • Page 36: Table 1-11: Clock Channel Group Assignments

    Getting Started Table 1–10: Misc channel group assignments (Cont.) Socket 7 order signal name Section:channel C3:4 BRDY# Indicates the channel is asserted LOW. Table 1–11 lists the probe section and channel assignments for the clock probes and the Socket 7 signal to which each channel connects. Table 1–11: Clock channel group assignments Socket 7 Section:channel...

  • Page 37: Table 1-12: Signals Not Required For Clocking Or Disassembly

    Getting Started Table 1–12 lists channel groups not required for clocking and disassembly. Table 1–12: Signals not required for clocking or disassembly Signal name TLA700 Channel C3:2 BRDY# C3:4 CACHE# C0:5 Indicates the channel is asserted low. Table 1–13 lists signals on the probe adapter but not acquired. Table 1–13: Signals on the probe adapter but not acquired Signal name AUX J580 Pin number...

  • Page 38: Cpu To Mictor Connections

    Tables 1–15 through 1–17 show the CPU pin to Mictor pin connections. Tektronix uses a counterclockwise pin assignment. Pin 1 is located at the top left, and pin 2 is located directly below it. Pin 20 is located on the bottom right, and pin 21 is located directly above it.

  • Page 39: Table 1-15: Cpu To Mictor Connections For Mictor A Pins

    Getting Started Table 1–15: CPU to Mictor connections for Mictor A pins Tektronix Socket 7 Socket 7 Mictor A Mictor A LA channel signal name pin number pin number pin number CLOCK:0 DVALID_D DERIVED A3:7 AJ-33 A3:6 AM-36 A3:5 AK-34...

  • Page 40: Table 1-16: Cpu To Mictor Connections For Mictor D Pins

    Getting Started Table 1–15: CPU to Mictor connections for Mictor A pins (Cont.) Tektronix Socket 7 Socket 7 Mictor A Mictor A signal name pin number pin number pin number LA channel CLOCK:1 PIPE_D DERIVED Table 1–16: CPU to Mictor connections for Mictor D pins...

  • Page 41: Table 1-17: Cpu To Mictor Connections For Mictor E Pins

    Getting Started Table 1–16: CPU to Mictor connections for Mictor D pins (Cont.) Tektronix Socket 7 Socket 7 Mictor D Mictor D signal name pin number pin number pin number LA channel D0:1 G-35 D0:2 J-35 D0:3 G-33 D0:4 F-36...
  • Page 42 Getting Started Table 1–17: CPU to Mictor connections for Mictor E pins (Cont.) Tektronix Socket 7 Socket 7 Mictor E Mictor E signal name pin number pin number pin number LA channel E3:5 L-03 E3:4 L-05 E3:3 K-04 E3:2 J-05...

  • Page 43: Table 1-18: Cpu To Mictor Connections For Mictor C Pins

    Getting Started Table 1–17: CPU to Mictor connections for Mictor E pins (Cont.) Tektronix Socket 7 Socket 7 Mictor E Mictor E signal name pin number pin number pin number LA channel Table 1–18: CPU to Mictor connections for Mictor C pins...
  • Page 44 Getting Started Table 1–18: CPU to Mictor connections for Mictor C pins (Cont.) Tektronix Socket 7 Socket 7 Mictor C Mictor C signal name pin number pin number pin number LA channel C0:7 DERIVED C1:0 AL-09 C1:1 AK-10 C1:2 AL-11...

  • Page 45: Operating Basics

    Operating Basics...

  • Page 47: Setting Up The Support

    Symbol table files Remember that the information in this section is specific to the operations and functions of the TMS 109A Socket 7 support on any Tektronix logic analyzer for which it can be purchased. Information on basic operations describes general tasks and functions.

  • Page 48: Figure 2-1: Nonpipelined Single And Burst Transfer Cycles

    Setting Up the Support Figure 2–1 shows two typical bus cycles: a single cycle transfer followed by a burst transfer. The ADS#, Address and Data signal forms are delayed by two CLK cycles. This diagram also shows the timing relationships of LAST_D and DVALID_D, the signals synthesized by sequential logic in the PALs.

  • Page 49: Clockingoptions

    Setting Up the Support DVALID_D, and PIPE_D, which are the signals synthesized by sequential logic in the PALs. Latched ADS# Delayed Address Delayed Data LAST_D DVALID_D PIPE_D Sample point 1 Master sample Master sample Sample point 1 A31-A0 D63-D0 D63-D0 A31-A0 M/IO# All other...
  • Page 50 Setting Up the Support Alternate Bus Master Cycles Excluded. Whenever the HLDA signal is high, no bus cycles are logged in. Only bus cycles driven by the microprocessor (HLDA low) will be logged in. Backoff cycles (caused by the BOFF# signal) are stored. Alternate Bus Master Cycles Included.

  • Page 51: Mode Differences

    Setting Up the Support Mode Differences The Socket 7 microprocessor can operate in either Component or Chip Set mode. Component Mode In Component mode (stand alone), the microprocessor interfaces directly to the system bus. Chip Set Mode The Socket 7 microprocessor, C5C cache controller, and the C8C cache memory (SRAM) can be combined to form a chip set or enhanced design.
  • Page 52 Setting Up the Support Table 2–1: Control group symbol table definitions (cont.) Control group value PRDY SCYC BOFF3# D/P# BUSCHK# LAST_D M/IO# INIT SMIACT# AHOLD D/C# Symbol Meaning IRESET_L LOCK# HLDA W/R# Opcode read Primary processor locked read cycle Dual processor locked read cycle Locked read cycle Primary processor locked write cycle Dual processor locked write cycle...
  • Page 53 Setting Up the Support Table 2–1: Control group symbol table definitions (cont.) Control group value PRDY SCYC BOFF3# D/P# BUSCHK# LAST_D M/IO# INIT SMIACT# AHOLD D/C# Symbol Meaning IRESET_L LOCK# HLDA W/R# Dual processor int. acknowledge Interrupt acknowledge cycle Primary processor special cycle Dual processor special cycle Special cycle Primary processor reserved...
  • Page 54 Setting Up the Support 2–8 TMS 109A Socket 7 Microprocessor Support...

  • Page 55: Acquiring And Viewing Disassembled Data

    However, you can reliably conduct timing analysis of nonIntel Socket 7 processors and use the high-level source debug capabilities of a Tektronix logic analyzer. Consult your Tektronix field office for future enhancements.

  • Page 56: Table 2-2: Meaning Of Special Characters In The Display

    Acquiring and Viewing Disassembled Data The default display format shows the Address, Data, Data_Lo, and Control channel groups for each sample of acquired data. The Data and Data_Lo groups are shown in one column. The disassembler displays special characters and strings in the instruction mnemonics to indicate significant events.
  • Page 57 Acquiring and Viewing Disassembled Data Table 2–2: Meaning of special characters in the display (cont.) Character or string displayed Meaning This notation will be placed in a mnemonic field if the disassembler views the operand invalid for the instruction. For example, there is not a control register named “CR7”. Thus if the operand byte would indicate the register “CR7”, “(??)”...

  • Page 58: Timing-Waveform Display Format

    Acquiring and Viewing Disassembled Data Timing-Waveform Display In the Timing-Waveform display format, the display is set up to show the Format following waveforms: D/C# RESET Address M/IO# HLDA DataData_Lo BOFF# ADS# CACHE# AHOLD D/P# BRDY# W/R# LOCK# Hardware Display Format In Hardware display format, the disassembler displays certain cycle type labels in parentheses (see Figure 2–9 on page 2–23).
  • Page 59 Acquiring and Viewing Disassembled Data Table 2–3: Cycle type definitions (Cont.) Label Description Reserved Bus is released to an Alternate Bus Master Back Off bus cycle An invalid/unknown bus cycle Fetch cycle computed to be a burst fill. The data is fetched but will not be executed, it is part of a 32 byte fetch.

  • Page 60: Figure 2-3: Hardware Display Format

    Acquiring and Viewing Disassembled Data Figure 2–3 shows an example of the Hardware display. Figure 2–3: Hardware display format Sample Column. Lists the memory locations for the acquired data. Address Group. Lists data from channels connected to the Socket 7 address bus.
  • Page 61 Acquiring and Viewing Disassembled Data Software Display Format The Software display format shows only the first fetch of executed instructions. Flushed cycles and extensions are not shown, even though they are part of the executed instruction. Read extensions will be used to disassemble the instruction, but will not be displayed as a separate cycle in the Software display format.
  • Page 62 Acquiring and Viewing Disassembled Data MMX. Instructions that generate a trap in the flow of control in the Socket 7 microprocessor are as follows: IRET CALL Instructions that might generate a conditional trap in the flow of control in the Socket 7 microprocessor are as follows: EMMS MOVD...
  • Page 63 Acquiring and Viewing Disassembled Data PADDW PAND PANDN PCMPEQB PCMPEQD PCMPEQW PCMPGTB PCMPGTD PCMPGTW PMADDWD PMULHW PMULLW PSLLD PSLLQ PSLLW PSRAD PSRAW PSRLD PSRLQ PSRLW PSUBB PSUBD PSUBSB PSUBSW PSUBUSB PSUBUSW PSUBW PUNPCKHBW PUNPCKHDQ PUNPCKHWD PUNPCKLBW PUNPCKLDQ PUNPCKLWD PXOR Changing How Data is Displayed There are common fields and features that allow you to further modify displayed data to suit your needs.
  • Page 64 Acquiring and Viewing Disassembled Data The Socket 7 support has six additional fields: Code Segment Size, Interrupt Table, Interrupt Table Address, Interrupt Table Size, Trace Processor, and Other Processor. These fields appear in the area indicated in the information on basic operations.

  • Page 65: Figure 2-4: Data Displayed From The Primary And Dual Microprocessors

    Acquiring and Viewing Disassembled Data Table 2–4: Trace Processor and Other Processor field selections Trace processor Other processor Effect Primary Suppress Disassemble the Primary microprocessor only Primary Display Cycles Disassemble the Primary microprocessor and display the hardware cycles of the Dual microprocessor Dual Suppress...

  • Page 66: Figure 2-5: Disassembled Data Displayed From The Primary Microprocessor Only

    Acquiring and Viewing Disassembled Data Figure 2–5 shows disassembled data from the Primary microprocessor only. Data from the Dual microprocessor is suppressed and not displayed. Figure 2–5: Disassembled data displayed from the Primary microprocessor only Figure 2–6 shows disassembled data from the Dual microprocessor only. Data from the Primary microprocessor is suppressed and not displayed.

  • Page 67: Figure 2-7: Display Of Target And Source Branch Trace Messages

    Acquiring and Viewing Disassembled Data Branch Trace Messages The disassembler interprets the information on the Address and Data Bus of Branch Trace Messages (BTMs) by reconstructing the address of the source or target of the branch instruction. Depending on which type of BTM is in use, either fast or normal, one or two BTMs will appear on the bus.

  • Page 68: Figure 2-8: Software Display For The Amd Bus Cycles

    Acquiring and Viewing Disassembled Data In the Hardware display format, you can determine the executed order of the out-of-order fetches by looking at the address of the out-of-order cycles and the subsequent cycles. Fetch cycles always have the sample numbers displayed. In the Software display format, out-of-order fetches are displayed in the order they were executed (see Figure 2–8).

  • Page 69: Figure 2-9: Hardware Display For The Amd Bus Cycles

    Acquiring and Viewing Disassembled Data Figure 2–9: Hardware display for the AMD Bus cycles Speculative Prefetch Speculative prefetch cycles can occur when the Socket 7 microprocessor fetches Cycles instructions that have been previously executed. To minimize prefetch delays, the Socket 7 microprocessor predicts the outcome of the branch instruction and starts prefetching at that address.

  • Page 70: Figure 2-10: Speculative Prefetch Cycles

    Acquiring and Viewing Disassembled Data not taken, flushed the speculative prefetch cycles, and started fetching at 0x38988 (sample 750), which contained the next instruction after the JNE. Figure 2–10: Speculative Prefetch cycles NOTE. The microprocessor also has a Branch Target Buffer and often performs speculative prefetching of branch target addresses (no matter if they are taken or are not taken).
  • Page 71 Acquiring and Viewing Disassembled Data separate, alternate memory space called SMRAM. The disassembler uses information from the SMIACT# signal to determine when the Socket 7 micropro- cessor is operating in this mode. MMX Instruction Set The Socket 7 microprocessor includes the MMX instruction set. Since these instructions are potential subroutine instructions, the disassembler checks to see if an interrupt level 6 (illegal opcode) or 7 (device not available) occurred.

  • Page 72: Table 2-5: Exception Vectors For Real Addressing Mode

    Acquiring and Viewing Disassembled Data You can use the Mark Opcode function to specify the default segment size mode (16-bit or 32-bit) for the cycle. The segment size selection changes the cycle the cursor is on and the remaining cycles to the end of memory or to the next mark. The default segment size of the cycle is independent of any prefix override bytes in the particular fetch.

  • Page 73: Table 2-6: Exception Vectors For Protected Addressing Mode

    Acquiring and Viewing Disassembled Data Table 2–5: Exception vectors for Real Addressing mode (cont.) Exception Location in IV* table number (in hexadecimal) Displayed interrupt name 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0034 14-15 0038-003C 0040 17-31 0044-007C 32-255 0080-03FC...
  • Page 74 Acquiring and Viewing Disassembled Data Table 2–6: Exception vectors for Protected Addressing mode (cont.) Exception Location in IDT* number (in hexadecimal) Displayed exception name 0060 0068 0070 0078 0080 0088 0090 19-31 0090-00F8 32-255 0100-07F8 IDT means interrupt descriptor table. Viewing an Example of Disassembled Data A demonstration system file (or demonstration reference memory) is provided so you can see an example of how your Socket 7 microprocessor bus cycles and...
  • Page 75 Specifications...
  • Page 77 Specifications This chapter contains the following information: Probe adapter description Specification tables Dimensions of the probe adapter Probe Adapter Description The probe adapter is nonintrusive hardware that allows the logic analyzer to acquire data from a microprocessor in its own operating environment with little effect, if any, on that system.

  • Page 78: Table 3-1: Electrical Specifications

    Specifications Specifications These specifications are for a probe adapter connected between a compatible Tektronix logic analyzer and a system under test. Table 3–1 shows the electrical requirements the system under test must produce for the support to acquire correct data.

  • Page 79: Table 3-2: Environmental Specifications

    15 km (50,000 ft) maximum Electrostatic immunity The probe adapter is static sensitive Designed to meet Tektronix standard 062-2847-00 class 5. Not to exceed Socket 7 microprocessor thermal considerations. Forced air cooling might be required across the CPU. TMS 109A Socket 7 Microprocessor Support...

  • Page 80: Figure 3-1: Dimensions Of The Probe Adapter

    Specifications Figure 3–1 shows the dimensions of the probe adapter. 51.05 mm (2.010 in) Pin A3 40.64 mm (1.600 in) 118.87 mm (4.680 in) 121.41 mm (4.780 in) 6.60 mm (.260 in) Figure 3–1: Dimensions of the probe adapter 3–4 TMS 109A Socket 7 Microprocessor Support...
  • Page 81 WARNING The following servicing instructions are for use only by qualified personnel. To avoid injury, do not perform any servicing other than that stated in the operating instructions unless you are qualified to do so. Refer to all Safety Summaries before performing any service.
  • Page 83 Maintenance...
  • Page 85 Maintenance This chapter contains information on the following topics: Probe adapter circuit description How to replace a fuse Probe Adapter Circuit Description The active components on the probe adapter are: five GAL 22V10D PALs for signal synthesis, one LM3940ISX for 5 V to 3.3 V conversion, and one PPL-Buffer and one PLL (phase locked loop) low-skew clock generator for clock distribution with buffer.

  • Page 86: Figure 4-1: Location Of The Fuse On The Probe Adapter

    Maintenance A PLL clock generator is used to provide eight, zero-delay copies of the Socket 7 microprocessor CLK input that are distributed to the PALs. Lock time after VCC is a 500 S maximum, the clock is stable before any Socket 7 microprocessor bus cycles start.
  • Page 87 Diagrams...
  • Page 89 The circuit board illustration appears only once; its lookup table lists the diagram number of all diagrams on which the circuitry appears. Other standards used in the preparation of diagrams by Tektronix, Inc., include the following: Some of the circuit board component location illustrations are expanded and divided into several parts to make it easier for you to locate small components.
  • Page 90 TMS 109A Socket 7 Hardware Support 5–2...
  • Page 91 TMS 109A Socket 7 Microprocessor Support 5–3...
  • Page 92 A1 Socket 7 Circuit Board (Front) A1 Socket 7 Circuit Board (Back) TMS 109A Socket 7 Microprocessor Support 5–4...
  • Page 93 TMS 109A Socket 7 Microprocessor Support 5–5...
  • Page 94 TMS 109A Socket 7 Microprocessor Support 5–6...
  • Page 95 TMS 109A Socket 7 Microprocessor Support 5–7...
  • Page 96 TMS 109A Socket 7 Microprocessor Support 5–8...
  • Page 97 TMS 109A Socket 7 Microprocessor Support 5–9...
  • Page 98 TMS 109A Socket 7 Microprocessor Support 5–10...
  • Page 99 TMS 109A Socket 7 Microprocessor Support 5–11...
  • Page 100 TMS 109A Socket 7 Microprocessor Support 5–12...
  • Page 101 Replaceable Parts...
  • Page 103 This section contains a list of the replaceable parts for the TMS 109A Socket 7 microprocessor support product. Parts Ordering Information Replacement parts are available through your local Tektronix field office or representative. Changes to Tektronix products are sometimes made to accommodate improved components as they become available and to give you the benefit of the latest improvements.
  • Page 104 91–3 COLIN DRIVE HOLBROOK, NY 11741 63058 BERG ELECTRONICS INC. MCKENZIE SOCKET DIV FREMONT, CA 94538–7340 910 PAGE AVE 80009 TEKTRONIX INC 14150 SW KARL BRAUN DR BEAVERTON, OR 97077–0001 PO BOX 500 82389 SWITCHCRAFT DIV OF RAYTHEON CHICAGO, IL 60630–1314 5555 N.
  • Page 105 Replaceable Parts Replaceable parts list Fig. & Tektronix Serial no. Serial no. index part number effective discont’d Name & description Mfr. code Mfr. part number number 6–1–0 010–0614–00 ADAPTER,PROBE SOCKET–7, SOCKETED, 80009 010–0614–00 PGA–321 PIN;TMS109A –1 671–4737–00 CIRCUIT BOARD:SOCKET–7,SOCKETED,PGA–321 80009 671–4737–00...
  • Page 106 Replaceable Parts Replaceable parts list (cont.) Fig. & Tektronix Serial no. Serial no. index part number effective discont’d Name & description Mfr. code Mfr. part number number 161–0104–07 CA ASSY,PWR:3,1.0MM SQ,240V/10A,2.5 TK2541 ORDER BY METER,RTANG,IEC320,RCPT X 13A,FUSED,UK DESCRIPTION PLUG,(13A FUSE) 161–0167–00...

  • Page 107: Figure 6-1: Tms 109A Socket 7 Probe Adapter Exploded View

    Replaceable Parts Figure 6–1: TMS 109A Socket 7 probe adapter exploded view 6–5 TMS 109A Socket 7 Microprocessor Support...
  • Page 108 Replaceable Parts 6–6 TMS 109A Socket 7 Microprocessor Support...
  • Page 109 Index...
  • Page 111 Index Numbers clock channel assignments, 1–21 clock rate, 1–2 3DNow! instruction set, 2–25 clocking, Custom, how data is acquired, 2–1 40 MHz system under test, 1–4 Code Segment Size field, 2–18 connections CPU to Mictor, 1–22 microprocessor removal, 1–7 probe adapter to SUT, 1–6 about this manual set, ix sockets, 1–8 acquiring data, 2–9...
  • Page 112 Index display, multiple lines for one sample, 2–11 display formats Control Flow, 2–15 logic analyzer Hardware, 2–12 configuration for disassembler, 1–1 Software, 2–15 software compatibility, 1–1 special characters, 2–10 Subroutine, 2–16 dual processor tracing, 2–18 dual processors execution tracing, 2–18 manual conventions, ix how to use the set, ix...
  • Page 113 Index Probe Mode cycles, 1–3 <more>, 2–22 Processor Selection Jumper, 1–5 > indicates insufficient room on screen, 2–10 >> indicates manually marked fetch program, 2–10 c indicates cache invalidation, 2–24 SMM indicates system mode cycle, 2–10 t indicates number is in decimal, 2–10 reads/writes, 1–3 special characters displayed, 2–10 reference memory, 2–28...

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