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PCM1796
SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006
PCM1796DBR Pin Discriptions
TERMINAL
NAME
PIN
AGND1
19
AGND2
24
AGND3L
27
AGND3R
16
BCK
6
DATA
5
DGND
8
I OUT L+
25
I OUT L–
26
I OUT R+
17
I OUT R–
18
I REF
20
LRCK
4
MC
12
MDI
11
MDO
13
MS
10
MSEL
3
RST
14
SCK
7
V CC 1
23
V CC 2L
28
V CC 2R
15
V COM L
22
V COM R
21
V DD
9
ZEROL
1
ZEROR
2
(1) Schmitt-trigger input, 5-V tolerant
(2) Schmitt-trigger input and output. 5-V tolerant input and CMOS output
(3) Schmitt-trigger input and output. 5-V tolerant input. In I 2 C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a CMOS
output.
6
Terminal Functions
I/O
I/O
–
Analog ground (internal bias)
–
Analog ground (internal bias)
–
Analog ground (L-channel DACFF)
–
Analog ground (R-channel DACFF)
Bit clock input (1)
I
Serial audio data input (1)
I
–
Digital ground
O
L-channel analog current output+
O
L-channel analog current output–
O
R-channel analog current output+
O
R-channel analog current output–
–
Output current reference bias pin
Left and right clock (f S ) input (1)
I
Mode control clock input (1)
I
Mode control data input (1)
I
Mode control readback data output (3)
I/O
Mode control chip-select input (2)
I/O
I 2 C/SPI select (1)
I
Reset (1)
I
System clock input (1)
I
–
Analog power supply, 5 V
–
Analog power supply (L-channel DACFF), 5 V
–
Analog power supply (R-channel DACFF), 5 V
–
L-channel internal bias decoupling pin
–
R-channel internal bias decoupling pin
–
Digital power supply, 3.3 V
Zero flag for L-channel (2)
I/O
Zero flag for R-channel (2)
I/O
DESCRIPTIONS
DESCRIPTIONS
74
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