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TAS5611PHD (MAIN : IC109)
www.ti.com
Block Diagram
FUNCTIONAL BLOCK DIAGRAM
/CLIP
READY
/OTW1
/OTW2
/SD
M1
M2
M3
/RESET
C_STARTUP
OSC_SYNC_IO+
OSC_SYNC_IO-
FREQ_ADJ
PSU_REF
VI_CM
INPUT_A
INPUT_B
INPUT_C
INPUT_D
Copyright © 2009, Texas Instruments Incorporated
OC_ADJ
1
RESET
2
C_STARTUP
3
INPUT_A
4
INPUT_B
5
VI_CM
6
GND
7
AGND
8
VREG
9
INPUT_C
10
INPUT_D
11
FREQ_ADJ
12
OSC_IO+
13
OSC_IO-
14
SD
15
OTW1
16
STARTUP
CONTROL
OSCILLATOR
4
PVDD_X
PSU_FF
GND
-
ANALOG
+
LOOP FILTER
+
ANALOG
-
LOOP FILTER
-
ANALOG
+
LOOP FILTER
+
ANALOG
-
LOOP FILTER
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
POWER-UP
RESET
TEMP
GVDD_A
SENSE
GVDD_B
OVER-LOAD
PROTECTION
4
PVDD_X
4
PPSC
OUT_X
4
GND_X
PWM
ACTIVITY
DETECTOR
PWM
TIMING
CONTROL
RECEIVER
CONTROL
PWM
TIMING
CONTROL
RECEIVER
CONTROL
PWM
TIMING
CONTROL
RECEIVER
CONTROL
PWM
TIMING
CONTROL
RECEIVER
CONTROL
80
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GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
TAS5611
SLAS681 – NOVEMBER 2009
VDD
UVP
VREG
VREG
AGND
GVDD _C
GND
GVDD_D
CURRENT
CB3C
OC_ADJ
SENSE
GVDD_A
BST_A
PVDD_A
GATE-DRIVE
OUT_A
GND_A
GVDD_B
BST_B
PVDD_B
GATE-DRIVE
OUT_B
GND_B
GVDD_C
BST_C
PVDD_C
GATE-DRIVE
OUT_C
GND_C
GVDD_D
BST_D
PVDD_D
GATE-DRIVE
OUT_D
GND_D
9
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