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PIN CONFIGURATIONS
54-Pin TSOP (Type II)
IS42S16400F-6TL (USB: IC4)
VDD
1
DQ0
2
VDDQ
3
DQ1
4
DQ2
5
GNDQ
6
DQ3
7
DQ4
8
VDDQ
9
DQ5
10
DQ6
11
GNDQ
12
DQ7
13
VDD
14
LDQM
15
WE
16
CAS
17
RAS
18
19
CS
BA0
20
BA1
21
A10
22
A0
23
A1
24
A2
25
A3
26
VDD
27
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Block Diagram
FUNCTIONAL BLOCK DIAGRAM
/CLIP
READY
/OTW1
/OTW2
/SD
WE
Write Enable
M1
M2
LDQM
Lower Bye, Input/Output Mask
M3
/RESET
UDQM
Upper Bye, Input/Output Mask
C_STARTUP
V
Power
DD
GND
Ground
OSC_SYNC_IO+
OSC_SYNC_IO-
FREQ_ADJ
V
Power Supply for DQ Pin
DDQ
GNDQ
Ground for DQ Pin
NC
No Connection
PSU_REF
VI_CM
INPUT_A
INPUT_B
INPUT_C
INPUT_D
Copyright © 2009, Texas Instruments Incorporated
54
GND
53
DQ15
52
GNDQ
51
DQ14
50
DQ13
49
VDDQ
48
DQ12
47
DQ11
46
GNDQ
45
DQ10
44
DQ9
43
VDDQ
42
DQ8
41
GND
40
NC
39
UDQM
38
CLK
37
CKE
36
NC
35
A11
34
A9
33
A8
32
A7
31
A6
30
A5
29
A4
28
GND
STARTUP
CONTROL
OSCILLATOR
4
PVDD_X
PSU_FF
GND
-
ANALOG
+
LOOP FILTER
+
ANALOG
-
LOOP FILTER
-
ANALOG
+
LOOP FILTER
+
ANALOG
-
LOOP FILTER
Product Folder Link(s):
POWER-UP
UVP
RESET
TEMP
GVDD_A
GVDD _C
SENSE
GVDD_B
GVDD_D
OVER-LOAD
CB3C
PROTECTION
4
PVDD_X
4
PPSC
OUT_X
4
GND_X
PWM
ACTIVITY
DETECTOR
PWM
TIMING
CONTROL
GATE-DRIVE
RECEIVER
CONTROL
1
PWM
TIMING
CONTROL
GATE-DRIVE
RECEIVER
CONTROL
PWM
TIMING
CONTROL
GATE-DRIVE
RECEIVER
CONTROL
PWM
TIMING
CONTROL
GATE-DRIVE
RECEIVER
CONTROL
Submit Documentation Feedback
TAS5611
82
TAS5611
SLAS681 – NOVEMBER 2009
VDD
VREG
VREG
AGND
GND
CURRENT
OC_ADJ
SENSE
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
GVDD_B
BST_B
PVDD_B
OUT_B
GND_B
GVDD_C
BST_C
PVDD_C
OUT_C
GND_C
GVDD_D
BST_D
PVDD_D
OUT_D
GND_D
9
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