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TAS5611
Block Diagram
SLAS681 – NOVEMBER 2009
PIN
NAME
PHD NO.
DKD NO.
AGND
8
10
BST_A
54
43
BST_B
41
34
BST_C
40
33
BST_D
27
24
CLIP
18
—
C_STARTUP
3
5
FREQ_ADJ
12
14
7, 23, 24, 57,
GND
9
58
GND_A
48, 49
38
GND_B
46, 47
37
GND_C
34, 35
30
GND_D
32, 33
29
GVDD_A
55
—
GVDD_B
56
—
GVDD_C
25
—
GVDD_D
26
—
GVDD_AB
—
44
GVDD_CD
—
23
INPUT_A
4
6
INPUT_B
5
7
INPUT_C
10
12
INPUT_D
11
13
M1
20
20
M2
21
21
M3
22
22
NC
59–62
–
OC_ADJ
1
3
OSC_IO+
13
15
OSC_IO–
14
16
OTW
—
18
OTW1
16
—
OTW2
17
—
OUT_A
52, 53
39, 40
OUT_B
44, 45
36
OUT_C
36, 37
31
OUT_D
28, 29
27, 28
PSU_REF
63
1
PVDD_A
50, 51
41, 42
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PVDD_B
42, 43
35
PVDD_C
38, 39
32
PIN
PVDD_D
30, 31
25, 26
NAME
PHD NO.
DKD NO.
READY
19
19
(1) I = Input, O = Output, P = Power
RESET
2
4
6
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SD
15
17
VDD
64
2
VI_CM
6
8
VREG
9
11
Copyright © 2009, Texas Instruments Incorporated
PIN FUNCTIONS
(1)
Function
DESCRIPTION
P
Analog ground
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
O
Clipping warning; open drain; active low
O
Startup ramp requires a charging capacitor of 4.7 nF to GND in BTL mode
I
PWM frame rate programming pin requires resistor to GND
P
Ground
P
Power ground for half-bridge A
P
Power ground for half-bridge B
P
Power ground for half-bridge C
P
Power ground for half-bridge D
P
Gate drive voltage supply requires 0.1 μF capacitor to GND_A
P
Gate drive voltage supply requires 0.1 μF capacitor to GND_B
P
Gate drive voltage supply requires 0.1 μF capacitor to GND_C
P
Gate drive voltage supply requires 0.1 μF capacitor to GND_D
P
Gate drive voltage supply requires 0.22 μF capacitor to GND_A/GND_B
P
Gate drive voltage supply requires 0.22 μF capacitor to GND_C/GND_D
I
Input signal for half bridge A
I
Input signal for half bridge B
I
Input signal for half bridge C
I
Input signal for half bridge D
I
Mode selection
I
Mode selection
I
Mode selection
—
No connect, pins may be grounded.
O
Analog overcurrent programming pin requires 30kΩ resistor to GND.
I/O
Oscillator master/slave output/input.
I/O
Oscillator master/slave output/input.
O
Overtemperature warning signal, open drain, active low.
O
Overtemperature warning signal, open drain, active low.
O
Overtemperature warning signal, open drain, active low.
O
Output, half bridge A
O
Output, half bridge B
O
Output, half bridge C
O
Output, half bridge D
P
PSU Reference requires close decoupling of 330 pF to GND
Power supply input for half bridge A requires close decoupling of 2uF capacitor
P
GND_A
Power supply input for half bridge B requires close decoupling of 2uF capacitor
P
GND_B
PIN FUNCTIONS (continued)
Power supply input for half bridge C requires close decoupling of 2uF
P
capacitor GND_C
Power supply input for half bridge D requires close decoupling of 2uF
(1)
Function
DESCRIPTION
P
capacitor GND_D
O
Normal operation; open drain; active high
I
Device reset Input; active low
O
Shutdown signal, open drain, active low
Product Folder Link(s):
Power supply for digital voltage regulator requires a 10-μF capacitor in parallel
TAS5611
P
with a 0.1-μF capacitor to GND for decoupling.
O
Analog comparator reference node requires close decoupling of 1nF to GND
P
Digital regulator supply filter pin requires 0.1-μF capacitor to GND
Product Folder Link(s):
TAS5611
www.ti.com
TAS5611
SLAS681 – NOVEMBER 2009
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
7
81
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