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M16C/65 Group
1.4
Block Diagram
Figure 1.3 to Figure 1.5 show block diagrams.
Block Diagram
Port P0
Internal peripheral functions
Three-phase motor control circuit
PWM function (8 bits X 2)
Remote control signal receiver
(10 bits X 26 channels)
Port P14
Notes :
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.3
Terminal Function
Pin
Pin Name
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
1
P9_4
IR
Page 10 of 791
2
P9_3
NC
3
P9_2
VFD_DIN
4
P9_1
VFD_RST
5
P9_0
VFD_CLK
6
BYTE
BYTL
7
CNVSS
CNVSS
8
P8_7
STBY_LED
9
P8_6
TIMER_LED
10
RESET
RESET
11
XOUT
XOUT
12
VSS
VSS
13
XIN
XIN
14
VCC1
VCC1
15
P8_5
MINI(PULL_UP)
16
P8_4
i-Pod_DET
8
8
8
Port P1
Port P2
Port P3
clock synchronous serial I/O
Timer (16-bit)
Outputs (timer A) : 5
Clock synchronous serial I/O
Inputs (timer B) : 6
Multi-master I
Real time clock
(2 circuits)
Watchdog timer
(15 bits X
1)
M16C/60 series CPU core
A/D converter
R0H
D/A converter
R1H
(8 bits X 2 channels)
VCC1 ports
Port P11
Port P10
2
8
8
Block Diagram (128 pins)
Symbol
I/O
Type
I
CMOS
O
CMOS
O
CMOS
O
CMOS
O
CMOS
I
-
-
-
O
CMOS
O
CMOS
-
-
-
-
-
-
-
-
-
-
I
N-channel
I
CMOS
8
8
8
Port P4
Port P5
Port P12
VCC2 ports
System clock generator
UART or
(6 channels)
PLL frequency synthesizer
On-chip oscillator (125 kHz)
High-speed on-chip oscillator
(8 bits x 2 channels)
2
C bus interface
(1 channel)
CEC function
CRC arithmetic circuit
Voltage detection circuit
R0L
SB
R1L
USP
R2
ISP
R3
INTB
A0
PC
A1
FB
FLG
Port P9
Port P8
Port P7
8
8
8
STBY
H
Remocon pulse input
L
NC
L
VFD Data out
L
VFD Reset
L
VFD Clock
L
GND(Ext. data bus bit width switching, 16bit:L)
Single-chip/Micro-processor mode switching(Normal
-
single-chip:L, Rewrite boot program start:H input set)
L
Standby LED On/Off
L
Timer Led On/Off
H
Reset input (reset:L)
-
Clock output
-
GND
-
Clock input
-
+3.3v
L
"H" fixed
L
iPod Dock Detect check
75
1. Overview
8
8
Port P13
XIN-XOUT
XCIN-XCOUT
DMAC
(4 channels)
(CCITT or CRC-16)
Power-on reset
On-chip debugger
Memory
(1)
ROM
RAM
(2)
Multiplier
Port P6
8
Note
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