The Effects Of Timing On Noise; Register Settings And Associated Timing Diagrams For Windowed Image Acquisition; Initial Configuration (Fpga, Asic) - Hand Held Products IT4000 Integration Manual

The Effects of Timing on Noise

IC Media has admitted that the settings and active area output timing selection can affect the noise levels within a given image.
Noise injection changes as the A/D samples are aligned with different points in the timing sequence. The best settings keep the
active pixels away from specific timing regions such as vertical and horizontal synchronization pulses which cause a flurry of
switching signal occurrences.

Register Settings and Associated Timing Diagrams for Windowed Image Acquisition

Initial Configuration (FPGA, ASIC)

The register settings of the initial Hand Held Products configuration are shown in the following table. The configuration generates
timing signals that create data acquisition windows for frame (vertical) and horizontal (row, line) data valid regions. The timing
is based on the IC Media default frame height and line width that provide a frame rate of 30 fps.
Initial Hand Held Products Register Settings for IC Media ICM105A
Register
Timing Control
Frame Width (pclk)
Frame Height (lines)
1
Beg act pix out (pclk)
Beg act frame out (lines) 1
Horiz pulse width (pclk)
Vert Pulse Width (lines)
CDS subt pulse pos (pclk)
Must be FW - 1 or placed after last active pixel
Exp time (pclk)
1. These values may be changed to meet the hardware timing requirements of the host
system.
2 - 6
Initial Hand Held
Hex
Products
Address
Hex Dec
02, 01 001B
0D, 0C 035A 858
0F, 0E 020D 525
11,10 0355 853
15, 14 0208 520
19, 18 0280 640
1B, 1A 01E0 480
9C, 9B 0342 834
1D, 1C FF00 65280
IMAGETEAM™ 4X00 Series Integration Manual
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