Linear Technology LTC2175-12 Manual

FeaTures
4-Channel Simultaneous Sampling ADC
n
70.6dB SNR
n
88dB SFDR
n
Low Power: 545mW/439mW/369mW Total,
n
136mW/110mW/92mW per Channel
Single 1.8V Supply
n
Serial LVDS Outputs: 1 or 2 Bits per Channel
n
Selectable Input Ranges: 1V
n
800MHz Full Power Bandwidth S/H
n
Shutdown and Nap Modes
n
Serial SPI Port for Configuration
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Pin Compatible 14-Bit and 12-Bit Versions
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52-Pin (7mm × 8mm) QFN Package
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applicaTions
Communications
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Cellular Base Stations
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Software Defined Radios
n
Portable Medical Imaging
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Multichannel Data Acquisition
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Nondestructive Testing
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V
CHANNEL 1
12-BIT
S/H
ANALOG
ADC CORE
INPUT
CHANNEL 2
12-BIT
ANALOG S/H
ADC CORE
INPUT
CHANNEL 3
12-BIT
ANALOG S/H
ADC CORE
INPUT
CHANNEL 4
12-BIT
ANALOG S/H
ADC CORE
INPUT
ENCODE
PLL
INPUT
to 2V
P-P P-P
1.8V
V OV
DD DD
DATA
SERIALIZER
GND OGND
LTC2174-12/LTC2173-12
12-Bit, 125Msps/105Msps/
80Msps Low Power Quad ADCs
DescripTion
The LTC 2175-12/LTC2174-12/LTC2173-12 are 4-channel,
®
simultaneous sampling 12-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 70.6dB SNR and
88dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.15ps allows undersampling of IF frequencies with
RMS
excellent noise performance.
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.3LSB
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode). The LVDS drivers have
optional internal termination and adjustable output levels
to ensure clean signal integrity.
+
The ENC and ENC
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
OUT1A
OUT1B
OUT2A
OUT2B
SERIALIZED
OUT3A
LVDS
OUT3B
OUTPUTS
OUT4A
–100
OUT4B
–110
DATA
–120
CLOCK
OUT
FRAME
217512 TA01
LTC2175-12/
.
RMS
–
inputs may be driven differentially
LTC2175-12, 125Msps,
2-Tone FFT, f = 70MHz and 75MHz
IN
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0 10 20 30 40
FREQUENCY (MHz)
50 60
217512 TA01b
21754312fa
1