Linear Technology LTC2172-12 Manual

FeaTures
4-Channel Simultaneous Sampling ADC
n
71dB SNR
n
90dB SFDR
n
Low Power: 306mW/198mW/160mW Total,
n
77mW/50mW/40mW per Channel
Single 1.8V Supply
n
Serial LVDS Outputs: One or Two Bits per Channel
n
Selectable Input Ranges: 1V
n
800MHz Full Power Bandwidth Sample-and-Hold
n
Shutdown and Nap Modes
n
Serial SPI Port for Configuration
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Pin-Compatible 14-Bit and 12-Bit Versions
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52-Pin (7mm × 8mm) QFN Package
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applicaTions
Communications
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Cellular Base Stations
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Software Defined Radios
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Portable Medical Imaging
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Multichannel Data Acquisition
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Nondestructive Testing
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V
CHANNEL 1
12-BIT
ANALOG S/H
ADC CORE
INPUT
CHANNEL 2
12-BIT
ANALOG S/H
ADC CORE
INPUT
CHANNEL 3
12-BIT
ANALOG S/H
ADC CORE
INPUT
CHANNEL 4
12-BIT
ANALOG S/H
ADC CORE
INPUT
ENCODE
PLL
INPUT
25Msps Low Power Quad ADCs
to 2V
P-P P-P
1.8V
V OV
DD DD
DATA
SERIALIZER
GND OGND
LTC2171-12/LTC2170-12
12-Bit, 65Msps/40Msps/
DescripTion
The LTC 2172-12/LTC2171-12/LTC2170-12 are 4-channel,
®
simultaneous sampling 12-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 71dB SNR and 90dB
spurious free dynamic range (SFDR). An ultralow jitter of
0.15ps allows undersampling of IF frequencies with
RMS
excellent noise performance.
DC specifications include ±0.3LSB INL (typ), ±0.1LSB
DNL (typ) and no missing codes over temperature. The
transition noise is a low 0.3LSB
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode) or one bit at a time (1-lane mode). The LVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
+
and ENC
The ENC
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
OUT1A
OUT1B
OUT2A
OUT2B
SERIALIZED
OUT3A
LVDS
OUT3B
OUTPUTS
OUT4A
OUT4B
DATA
CLOCK
OUT
FRAME
217212 TA01
LTC2172-12/
.
RMS
–
inputs may be driven differentially
LTC2172-12, 65Msps,
2-Tone FFT, f = 70MHz and 75MHz
IN
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 20
10
FREQUENCY (MHz)
30
217212 TA01b
21721012fb
1