HP Vectra XW Technical Reference Manual page 48

4 HP BIOS
BIOS Addresses
DMA Channel Controllers
Only "I/O-to-memory" and "memory-to-I/O" transfers are allowed.
"I/O-to-I/O" and "memory-to-memory" transfers are disallowed by the
hardware configuration.
The system controller supports seven DMA channels, each with a page
register used to extend the addressing range of the channel to 16 MB. The
following table summarizes how the DMA channels are allocated.
Channel
0
1
2
3
Second DMA controller (used for 16-bit transfers)
Channel
4
5
6
7
Interrupt Controllers
The system has two 8259A compatible interrupt controllers. They are
arranged as a master interrupt controller and a slave that is cascaded
through the master.
The following table shows how the master and slave controllers are con-
nected. The Interrupt Requests (IRQ) are numbered sequentially, starting
with the master controller, and followed by the slave.
40
First DMA controller (used for 8-bit transfers)
Available
SoundBlaster or ECP mode for parallel port
Flexible disk I/O
ECP mode for parallel port or SoundBlaster
Cascade from first DMA controller
SoundBlaster or Available
Available
Available or SoundBlaster
Function
Function