HP Vectra VE4 Reference Manual page 16

The ATM provides an ISA compatible interrupt controller that incorporates the functionality of
two 82C59 interrupt controllers.
Power Management
The ATM ensures that power management meets the requirements of the EPA
(Environmental Protection Agency) Energy Star program.
Address Decoding
The ATM contains two decoders—one to decode PCI/CPU master cycles and DMA/ISA
master cycles, the other to handle the cycles with which the DMA/ISA master accesses the
PCI or onboard memory.
ATM I/O Addresses
These addresses are the internal non-configurable ATM register locations.
BIOS Memory Space
The 128 KB memory space is located at 000E0000h to 000FFFFFh (top of 1 MB).
Data Integrity
The processor uses functional redundancy checking to provide maximum error detection of
the processor and its interface. When functional redundancy checking is used, a second
processor (the checker) operates in lock step with the master's outputs and compares them
with the values it computes internally. An error signal is produced if a mismatch is detected.
Vectra 4E/xx Technical Reference 1 System Overview 16