Sata Connector - HP Compaq dc7100 DT Technical Reference Manual

Input/Output Interfaces
SATA Bus Master Control Registers
The SATA interface can perform PCI bus master operations using the registers listed in Table
5-5. These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI
configuration register 20h in the previous table. As indicated, these registers are virtually a copy
of those used by EIDE operations discussed in the EIDE section.
I/O Addr.
Offset
00h
02h
04h
08h
0Ah
0Ch

SATA Connector

The 7-pin SATA connector is shown in the figure below.
Figure 5-2. 7-Pin SATA Connector (on system board).
Pin Description
1 Ground
2 TX positive
3 TX negative
4 Ground
5 RX negative
5-6
Table 5-5.
IDE Bus Master Control Registers
Size
(Bytes) Register
1 Bus Master IDE Command (Primary)
1 Bus Master IDE Status (Primary)
4 Bus Master IDE Descriptor Pointer (Primary)
1 Bus Master IDE Command (Secondary)
2 Bus Master IDE Status (Secondary)
4 Bus Master IDE Descriptor Pointer (Secondary
Pin 1
A
Table 5-6.
7-Pin SATA Connector Pinout
Pin
6
7
A
B
--
Description
RX positive
Ground
Holding clip
Holding clip
--
361834-002
Default Value
00h
00h
0000 0000h
00h
00h
0000 0000h
Pin 7
B
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