Pci Express Bus Operation - HP Compaq dc7100 DT Technical Reference Manual

System Support
Device
PCI Connector Slot 1
PCI Connector Slot 2
PCI Connector Slot 3
PCI Connector Slot 4
NOTE:
[1]SFF, ST, MT, and CMT form factors only.
[2] CMT form factor with PCI expansion board
PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm
specified by the PCI specification. The bus parking policy allows for the current PCI bus owner
(excepting the PCI/ISA bridge) to maintain ownership of the bus as long as no request is asserted
by another agent. Note that most CPU-to-DRAM and AGP-to-DRAM accesses can occur
concurrently with PCI traffic, therefore reducing the need for the Host/PCI bridge to compete for
PCI bus ownership.

4.2.2 PCI Express Bus Operation

The PCI Express bus is a high-performace extension of the legacy PCI bus specification. The PCI
Express bus uses the following layers:
■
Software/driver layer
■
Transaction protocol layer
■
Link layer
■
Physical layer
Software/Driver Layer
The PCI Express bus maintains software compatibility with PCI 2.3 and earlier versions so that
there is no impact on existing operating systems and drivers. During system intialization, the PCI
Express bus uses the same methods of device discovery and resource allocation that legacy
PCI-based operating systems and drivers are designed to use. The use of PCI configuration space
and the programmability of I/O devices are also used in the same way as for legacy PCI buses.
The software/driver layer provides read and write requests to the transaction layer for handling a
data transfer.
Transaction Protocol Layer
The transaction protocol layer processes read and write requests from the software/driver layer
and generates request packets for the link layer. Each packet includes an identifier allowing any
required responcse packets to be directed to the originator.
PCI Express protocol supports the three legacy PCI address spaces (memory, I/O, configuration)
as well as a new message space. The message space allows in-band processing of interrupts
through use of the Message Signal Interrupt (MSI) introduced with the PCI 2.2 specification. The
MSI method eliminates the need for hard-wired sideband signals by incorporating those
functions into packets.
4-6
Table 4-3.
PCI Bus Mastering Devices
REQ/GNT Line
REQ0/GNT0
REQ1/GNT1
REQ2/GNT2
REQ3/GNT3
Note
[1]
[2]
[2]
361834-002 Technical Reference Guide