HP Compaq dc7100 DT Technical Reference Manual page 76

System Support
The remaining address lines are in an undefined state during the refresh cycle. The refresh
operations are driven by a 69.799-KHz clock generated by Interval Timer 1, Counter 1. The
refresh rate is 128 refresh cycles in 2.038 ms.
DMA Controller Registers
Table 4-11 lists the DMA Controller Registers and their I/O port addresses. Note that there is a
set of registers for each DMA controller.
Register
Status
Command
Mode
Write Single Mask Bit
Write All Mask Bits
Software DRQx Request
Base and Current Address—Ch 0
Current Address—Ch 0
Base and Current Word Count—Ch 0
Current Word Count—Ch 0
Base and Current Address—Ch 1
Current Address—Ch 1
Base and Current Word Count—Ch 1
Current Word Count—Ch 1
Base and Current Address—Ch 2
Current Address—Ch 2
Base and Current Word Count—Ch 2
Current Word Count—Ch 2
Base and Current Address—Ch 3
Current Address—Ch 3
Base and Current Word Count—Ch 3
Current Word Count—Ch 3
Temporary (Command)
Reset Pointer Flip-Flop (Command)
Master Reset (Command)
Reset Mask Register (Command)
4-18
Table 4-11.
DMA Controller Registers
Controller 1
008h
008h
00Bh
00Ah
00Fh
009h
000h
000h
001h
001h
002h
002h
003h
003h
004h
004h
005h
005h
006h
006h
007h
007h
00Dh
00Ch
00Dh
00Eh
361834-002
Controller 2 R/W
0D0h R
0D0h W
0D6h W
0D4h W
0DEh W
0D2h W
0C0h W
0C0h R
0C2h W
0C2h R
0C4h W
0C4h R
0C6h W
0C6h R
0C8h W
0C8h R
0CAh W
0CAh R
0CCh W
0CCh R
0CEh W
0CEh R
0DAh R
0D8h W
0DAh W
0DCh W
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