Ddr3 So-Dimm_1 - Clevo W970SUW Service Manual

Schematic Diagrams

DDR3 SO-DIMM_1

SO-DIMM A_0
D
Sheet 9 of 45
DDR3 SO-DIMM_1
C
Layout Note:
signal/space/signal:
85 ohm
3.3VS
B
VDDQ_VTT
C111
10u_6.3V_X5R_06
V_VDDQ_DIMM
C341
+
A
560u_2.5V_6.6*6.6*5.9
V_VDDQ_DIMM
C130
1u_6.3V_X5R_04
B - 10 DDR3 SO-DIMM_1
5 4
CHANGE TO STANDARD
JDIMM1A
[4] M_A_A[15:0]
M_A_A0 98
A0
M_A_A1 97
A1
M_A_A2 96
A2
M_A_A3 95
A3
M_A_A4 92
A4
M_A_A5 91
A5
M_A_A6 90
A6
M_A_A7 86
A7
M_A_A8 89
A8
M_A_A9 85
A9
M_A_A10
107
A10/AP
M_A_A11 84
A11
M_A_A12 83
A12/BC#
M_A_A13 119
A13
M_A_A14
80
A14
M_A_A15 78
A15
109
[4] M_A_BS0 BA0
108
[4] M_A_BS1 BA1
79
[4] M_A_BS2
BA2
114
[4] M_A_CS#0 S0#
121
[4] M_A_CS#1 S1#
101
[4] M_A_CLK_DDR0 CK0
103
[4] M_A_CLK_DDR#0
CK0#
102
[4] M_A_CLK_DDR1
CK1
104
[4] M_A_CLK_DDR#1 CK1#
73
[4] M_A_CKE0 CKE0
74
[4] M_A_CKE1
CKE1
115
[4] M_A_CAS#
CAS#
110
[4] M_A_RAS# RAS#
113
[4] M_A_WE# WE#
SA0_A_DIM0
197
SA0
SA1_A_DIM0 201
SA1
202
[10,15,27] SMB_CLK SCL
200
[10,15,27] SMB_DATA SDA
116
[4] M_A_ODT0
ODT0
120
[4] M_A_ODT1 ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
[4] M_A_DQS[7:0]
M_A_DQS0
12
DQS0
M_A_DQS1 29
DQS1
M_A_DQS2 47
DQS2
M_A_DQS3 64
DQS3
M_A_DQS4 137
DQS4
M_A_DQS5 154
DQS5
M_A_DQS6 171
DQS6
M_A_DQS7 188
DQS7
[4] M_A_DQS#[7:0]
M_A_DQS#0 10
RN10
DQS0#
10K_8P4R_04 M_A_DQS#1 27
DQS1#
1 8 SA1_A_DIM0 M_A_DQS#2 45
DQS2#
2 7 SA0_A_DIM0 M_A_DQS#3 62
DQS3#
SA0_A_DIM1 M_A_DQS#4
3 6 135
SA0_A_DIM1 [10]
DQS4#
4 5 SA1_A_DIM1 M_A_DQS#5 152
SA1_A_DIM1 [10]
DQS5#
M_A_DQS#6 169
DQS6#
M_A_DQS#7 186
DQS7#
91-93469-179
V_VDDQ_DIMM
C125 C117 C104 C110
C101
1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04
0.1u_10V_X5R_04
C98 C119 C109 C353 C90
10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06
C351 C356 C106 C360 C85
1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 *1u_6.3V_X5R_04 *1u_6.3V_X5R_04
5 4
3
V_VDDQ_DIMM
C357 C103 C359
0.1u_10V_X5R_04 *0.1u_10V_X5R_04 *0.1u_10V_X5R_04
M_A_DQ[63:0] [4]
5 M_A_DQ0
DQ0
7 M_A_DQ1
DQ1
15 M_A_DQ2 V_VDDQ_DIMM
DQ2
17 M_A_DQ3
DQ3
4 M_A_DQ4
DQ4
6 M_A_DQ5
DQ5
16 M_A_DQ6
DQ6
18 M_A_DQ7 C346 C348 C349
DQ7
21 M_A_DQ8 *0.1u_10V_X5R_04 *0.1u_10V_X5R_04 0.1u_10V_X5R_04
DQ8
23 M_A_DQ9
DQ9
M_A_DQ10
33
DQ10
35 M_A_DQ11
DQ11
22 M_A_DQ12
DQ12
24 M_A_DQ13 3.3VS
DQ13
M_A_DQ14
34
DQ14
36 M_A_DQ15
DQ15
39 M_A_DQ16
DQ16
41 M_A_DQ17
DQ17
51 M_A_DQ18
DQ18
53 M_A_DQ19
DQ19
40 M_A_DQ20
DQ20
42 M_A_DQ21
DQ21
50 M_A_DQ22
DQ22
52 M_A_DQ23
DQ23
57 M_A_DQ24
DQ24
59 M_A_DQ25
DQ25
3.3VS
67 M_A_DQ26
DQ26
M_A_DQ27
69
DQ27
56 M_A_DQ28
DQ28
58 M_A_DQ29
DQ29
68 M_A_DQ30
DQ30 [10]
M_A_DQ31
70
DQ31 [3,10]
129 M_A_DQ32
DQ32
131 M_A_DQ33
DQ33
141 M_A_DQ34
DQ34
143 M_A_DQ35
DQ35
130 M_A_DQ36
DQ36
132 M_A_DQ37
DQ37
140 M_A_DQ38
DQ38
142 M_A_DQ39
DQ39
147 M_A_DQ40
DQ40
149 M_A_DQ41
DQ41
157 M_A_DQ42
DQ42
159 M_A_DQ43
DQ43
M_A_DQ44
146
DQ44
148 M_A_DQ45
DQ45
158 M_A_DQ46
DQ46
160 M_A_DQ47
DQ47
M_A_DQ48
163
DQ48
165 M_A_DQ49
DQ49
175 M_A_DQ50
DQ50
177 M_A_DQ51
DQ51
164 M_A_DQ52 R74 0_04
DQ52
166 M_A_DQ53
DQ53
174 M_A_DQ54
DQ54
176 M_A_DQ55 Q3
DQ55
181 M_A_DQ56 *AO3402L
DQ56
183 M_A_DQ57 S D
[4] V_SM_VREF
DQ57
191 M_A_DQ58
DQ58
193 M_A_DQ59
DQ59
180 M_A_DQ60 R75
DQ60
M_A_DQ61
182 *1K_04
DQ61
192 M_A_DQ62
DQ62
194 M_A_DQ63
DQ63
[16,25,30,31,32] SUSB#
C99 C95
0.1u_10V_X5R_04 0.1u_10V_X5R_04
R90 0_04
Q5
*AO3402L
S D
[4] V_SA_DIMM_VREFDQ
C108 C89
R87
10u_6.3V_X5R_06 *10u_6.3V_X5R_06
*1K_04
[3,10,15] DRAMRST_CNTRL
C343
+
560u_2.5V_6.6*6.6*5.9
[3,6,10,11,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,35]
3
2 1
C86 C100
0.1u_10V_X5R_04 0.1u_10V_X5R_04
JDIMM1B
V_VDDQ_DIMM
75 44
VDD1 VSS16
76 48
VDD2 VSS17
C347 C350 81 49
VDD3 VSS18
0.1u_10V_X5R_04 82 54
*0.1u_10V_X5R_04
VDD4 VSS19
87 55
VDD5 VSS20
88 60
VDD6 VSS21
93 61
VDD7 VSS22
94 65
VDD8 VSS23
99 66
VDD9 VSS24
20mils 100 71
VDD10 VSS25
105 72
VDD11 VSS26
106 127
VDD12 VSS27
C120 111 128
VDD13 VSS28
C113 112 133
VDD14 VSS29
0.1u_10V_X5R_04 117 134
2.2u_6.3V_X5R_04
VDD15 VSS30
118 138
VDD16 VSS31
123 139
VDD17 VSS32
124 144
VDD18 VSS33
145
VSS34
199 150
VDDSPD VSS35
151
VSS36
77 155
NC1 VSS37
122 156
NC2 VSS38
R86 10K_04 125 161
NCTEST VSS39
162
VSS40
198 167
TS#_DIMM0_1 EVENT# VSS41
30 168
DDR3_DRAMRST# RESET# VSS42
172
VSS43
C115 *2.2u_6.3V_X5R_06 173
VSS44
C116 *0.1u_10V_X5R_04 1 178
VREF_DQ VSS45
126 179
VREF_CA VSS46
MVREF_DQ_DIMMA 184
VSS47
185
VSS48
2 189
VSS1 VSS49
V_VREF_CA_DIMM 3 190
VSS2 VSS50
8 195
VSS3 VSS51
C123 *2.2u_6.3V_X5R_06 9 196
VSS4 VSS52
13
VSS5
C124 0.1u_16V_Y5V_04 14
VSS6
19
VSS7
20 VDDQ_VTT
VSS8
25
VSS9
26 203
VSS10 VTT1
31 204
VSS11 VTT2
32
V_VDDQ_DIMM VSS12
37 GND1
VSS13 G1
38 GND2
VSS14 G2
43
VSS15
R71 91-93469-179
1K_1%_04
V_VREF_CA_DIMM
V_VREF_CA_DIMM [10]
C79
R72 CLOSE TO JDIMM1
0.1u_10V_X5R_04 1K_1%_04
R73
24.9_1%_04
V_VDDQ_DIMM
DIMM & TR A C E
R88
1K_1%_04
MVREF_DQ_DIMMA
C114
R89
0.1u_10V_X5R_04
1K_1%_04
R85
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
24.9_1%_04
Title Title Title
[09] DDR3 SO-DIMM_A_0 [09] DDR3 SO-DIMM_A_0 [09] DDR3 SO-DIMM_A_0
[3,5,10,34] V_VDDQ_DIMM
Size Size Size Document Number Document Number Document Number
[10,34] VDDQ_VTT 6-71-W54S0-D03 6-71-W54S0-D03 6-71-W54S0-D03
A3 A3 A3 6-7P-W5409-003 6-7P-W5409-003 6-7P-W5409-003
3.3VS
Date: Date: Date: Wednesday, April 09, 2014 Wednesday, April 09, 2014 Wednesday, April 09, 2014 Sheet Sheet Sheet 9 9 9
2 1
D
C
B
A
R e v R e v R e v
3.0 3.0 3.0
o f o f o f 45 45 45