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Schematic Diagrams
DDR3 SO-DIMM_1
SO-DIMM A_0
D
M_A_CLK_DDR0
M_A_CLK_DDR1
Sheet 9 of 46
DDR3 SO-DIMM_0
C
Layout Note:
signal/space/signal:
85 ohm
3.3VS
B
VDDQ_VTT
C508
C508
10u_6.3V_X5R_06
10u_6.3V_X5R_06
V_VDDQ_DIMM
+
+
C81
C81
*330u_2.5V_V_A
*330u_2.5V_V_A
A
V_VDDQ_DIMM
C62
C62
1u_6.3V_X5R_04
1u_6.3V_X5R_04
B - 10 DDR3 SO-DIMM_1
5
4
CHANGE TO STANDARD
JDIMM1A
JDIMM1A
4
M_A_A[15:0]
98
M_A_A0
A0
M_A_A1
97
A1
M_A_A2
96
A2
95
M_A_A3
A3
92
C65
C65
*10p_50V_NPO_04
*10p_50V_NPO_04
M_A_A4
A4
M_A_CLK_DDR#0
M_A_A5
91
A5
M_A_A6
90
A6
86
C66
C66
*10p_50V_NPO_04
*10p_50V_NPO_04
M_A_A7
A7
89
M_A_CLK_DDR#1
M_A_A8
A8
M_A_A9
85
A9
M_A_A10
107
A10/AP
84
M_A_A11
A11
83
M_A_A12
A12/BC#
M_A_A13
119
A13
M_A_A14
80
A14
78
M_A_A15
A15
109
4
M_A_BS0
BA0
108
4
M_A_BS1
BA1
79
4
M_A_BS2
BA2
114
4
M_A_CS#0
S0#
121
4
M_A_CS#1
S1#
101
4
M_A_CLK_DDR0
CK0
103
4
M_A_CLK_DDR#0
CK0#
102
4
M_A_CLK_DDR1
CK1
104
4
M_A_CLK_DDR#1
CK1#
73
4
M_A_CKE0
CKE0
74
4
M_A_CKE1
CKE1
115
4
M_A_CAS#
CAS#
110
4
M_A_RAS#
RAS#
113
4
M_A_WE#
WE#
SA0_A_DIM0
197
SA0
201
SA1_A_DIM0
SA1
202
10,21
SMB_CLK
SCL
200
10,21
SMB_DATA
SDA
116
4
M_A_ODT0
ODT0
120
4
M_A_ODT1
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
4
M_A_DQS[7:0]
12
M_A_DQS0
DQS0
29
M_A_DQS1
DQS1
M_A_DQS2
47
DQS2
M_A_DQS3
64
DQS3
137
M_A_DQS4
DQS4
154
M_A_DQS5
DQS5
M_A_DQS6
171
DQS6
M_A_DQS7
188
DQS7
4
M_A_DQS#[7:0]
10
RN10
RN10
M_A_DQS#0
DQS0#
10K_8P4R_04
10K_8P4R_04
M_A_DQS#1
27
DQS1#
1
8
SA1_A_DIM0
M_A_DQS#2
45
DQS2#
2
7
62
SA0_A_DIM0
M_A_DQS#3
DQS3#
3
6
135
SA0_A_DIM1
M_A_DQS#4
SA0_A_DIM1
10
DQS4#
4
5
SA1_A_DIM1
M_A_DQS#5
152
SA1_A_DIM1
10
DQS5#
M_A_DQS#6
169
DQS6#
186
M_A_DQS#7
DQS7#
DSIRK-20401 -TP5B
DSIRK-20401 -TP5B
V_VDDQ_DIMM
C522
C522
C514
C514
C511
C511
C521
C521
C220
C220
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
C75
C75
C80
C80
C69
C69
C48
C48
C78
C78
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
C76
C76
C79
C79
C74
C74
C50
C50
C83
C83
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
*1u_6.3V_X5R_04
*1u_6.3V_X5R_04
*1u_6.3V_X5R_04
*1u_6.3V_X5R_04
5
4
3
V_VDDQ_DIMM
C85
C85
C93
C93
C113
C113
0.1u_10V_X5R_04
0.1u_10V_X5R_04
*0.1u_10V_X5R_04
*0.1u_10V_X5R_04
*0.1u_10V_X5R_04
*0.1u_10V_X5R_04
M_A_DQ[63:0]
4
5
M_A_DQ0
DQ0
7
M_A_DQ1
DQ1
15
M_A_DQ2
DQ2
17
V_VDDQ_DIMM
M_A_DQ3
DQ3
4
M_A_DQ4
DQ4
6
M_A_DQ5
DQ5
16
M_A_DQ6
DQ6
18
M_A_DQ7
DQ7
21
M_A_DQ8
C150
C150
C160
C160
DQ8
23
M_A_DQ9
*0.1u_10V_X5R_04
*0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
DQ9
33
M_A_DQ10
DQ10
35
M_A_DQ11
DQ11
22
M_A_DQ12
DQ12
24
M_A_DQ13
0917
3.3VS
DQ13
34
M_A_DQ14
DEL C157
DQ14
36
M_A_DQ15
DQ15
39
M_A_DQ16
DQ16
41
M_A_DQ17
DQ17
51
M_A_DQ18
DQ18
53
M_A_DQ19
DQ19
40
M_A_DQ20
DQ20
42
M_A_DQ21
DQ21
50
M_A_DQ22
DQ22
52
M_A_DQ23
DQ23
57
M_A_DQ24
DQ24
59
M_A_DQ25
DQ25
67
M_A_DQ26
3.3VS
DQ26
69
M_A_DQ27
DQ27
56
M_A_DQ28
DQ28
58
M_A_DQ29
DQ29
68
M_A_DQ30
DQ30
10
70
M_A_DQ31
DQ31
3,10
129
M_A_DQ32
DQ32
131
M_A_DQ33
DQ33
141
M_A_DQ34
DQ34
143
M_A_DQ35
DQ35
130
M_A_DQ36
DQ36
4
132
M_A_DQ37
DQ37
140
M_A_DQ38
DQ38
142
M_A_DQ39
DQ39
147
M_A_DQ40
DQ40
149
M_A_DQ41
DQ41
157
M_A_DQ42
DQ42
159
M_A_DQ43
DQ43
146
M_A_DQ44
DQ44
148
M_A_DQ45
DQ45
158
M_A_DQ46
DQ46
160
M_A_DQ47
DQ47
163
M_A_DQ48
DQ48
165
M_A_DQ49
DQ49
175
M_A_DQ50
DQ50
177
M_A_DQ51
DQ51
164
M_A_DQ52
DQ52
166
M_A_DQ53
DQ53
174
M_A_DQ54
DQ54
176
M_A_DQ55
DQ55
181
M_A_DQ56
DQ56
183
M_A_DQ57
DQ57
191
M_A_DQ58
DQ58
193
M_A_DQ59
DQ59
180
M_A_DQ60
DQ60
182
M_A_DQ61
DQ61
192
M_A_DQ62
DQ62
194
M_A_DQ63
DQ63
C272
C272
C278
C278
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
C100
C100
C98
C98
10u_6.3V_X5R_06
10u_6.3V_X5R_06
*10u_6.3V_X5R_06
*10u_6.3V_X5R_06
C198
C198
+
+
560u_2.5V_6.6*6.6*5.9
560u_2.5V_6.6*6.6*5.9
3
2
1
5.2mm
C114
C114
C126
C126
6-86-24204-005
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
6-86-24204-002
JDIMM1B
JDIMM1B
V_VDDQ_DIMM
75
44
VDD1
VSS16
76
48
VDD2
VSS17
81
49
VDD3
VSS18
82
54
C167
C167
C168
C168
VDD4
VSS19
0.1u_10V_X5R_04
0.1u_10V_X5R_04
87
55
*0.1u_10V_X5R_04
*0.1u_10V_X5R_04
VDD5
VSS20
88
60
VDD6
VSS21
93
61
VDD7
VSS22
94
65
VDD8
VSS23
99
66
VDD9
VSS24
100
71
20mils
VDD10
VSS25
105
72
VDD11
VSS26
106
127
VDD12
VSS27
C29
C29
111
128
VDD13
VSS28
C30
C30
112
133
VDD14
VSS29
117
134
0.1u_10V_X5R_04
0.1u_10V_X5R_04
2.2u_6.3V_X5R_04
2.2u_6.3V_X5R_04
VDD15
VSS30
118
138
VDD16
VSS31
123
139
VDD17
VSS32
124
144
VDD18
VSS33
145
VSS34
199
150
VDDSPD
VSS35
151
VSS36
77
155
NC1
VSS37
122
156
NC2
VSS38
125
161
R23
R23
10K_04
10K_04
NCTEST
VSS39
162
VSS40
198
167
TS#_DIMM0_1
EVENT#
VSS41
30
168
DDR3_DRAMRST#
RESET#
VSS42
172
VSS43
C122
C122
1u_6.3V_X5R_04
1u_6.3V_X5R_04
173
VSS44
C116
C116
0.1u_10V_X5R_04
0.1u_10V_X5R_04
MVREF_DQ_DIMMA
1
178
VREF_DQ
VSS45
126
179
VREF_CA
VSS46
184
MVREF_DQ_DIMMA
VSS47
185
VSS48
2
189
VSS1
VSS49
MVREF_DIMA_0
3
190
VSS2
VSS50
8
195
C44
C44
1u_6.3V_X5R_04
1u_6.3V_X5R_04
VSS3
VSS51
C38
C38
0.1u_10V_X5R_04
0.1u_10V_X5R_04
9
196
VSS4
VSS52
13
VSS5
14
VSS6
19
C169
C169
1u_6.3V_X5R_04
1u_6.3V_X5R_04
VSS7
20
VDDQ_VTT
VSS8
25
VSS9
26
203
VSS10
VTT1
31
204
VSS11
VTT2
32
VSS12
37
GND1
VSS13
G1
38
GND2
VSS14
G2
43
VSS15
DSIRK-20401 -TP5B
DSIRK-20401 -TP5B
CLOSE TO JDIMM1
V_VDDQ_DIMM
1K_1%_04
1K_1%_04
R46
R46
R47
R47
*0_04
*0_04
MVREF_DIMA_0
4,10
V_VREF_CA_DIMM
R44
R44
C60
C60
C52
C52
1K_1%_04
1K_1%_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
0.1u_10V_X5R_04
R40
R40
24.9_1%_04
24.9_1%_04
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[09]DDR3 SO-DIMM_A_0
[09]DDR3 SO-DIMM_A_0
[09]DDR3 SO-DIMM_A_0
Size
Size
Size
Document Number
Document Number
Document Number
6-71-W65S0-D02
6-71-W65S0-D02
6-71-W65S0-D02
A3
A3
A3
6-7P-W65C4-002
6-7P-W65C4-002
6-7P-W65C4-002
Date:
Date:
Date:
Tuesday, November 11, 2014
Tuesday, November 11, 2014
Tuesday, November 11, 2014
Sheet
Sheet
Sheet
9
9
9
2
1
D
C
B
A
Rev
Rev
Rev
2.0
2.0
2.0
of
of
of
46
46
46
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