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RA8900 SA / CE
VLF
Write
Read
5) VDET ( Voltage Detection Flag ) bit
This flag bit indicates the status of temperature compensation. Its value changes from "0" to "1" when stop the
temperature compensation, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is
retained until a "0" is written to it.
When after powering up from 0 V this bit's value is "1".
VDET
Write
Read
8.2.7. Control register
Address
Control Register
0F, 1F
1)
The default value is the value that is read (or is set internally) after powering up from 0 V.
2)
"o" indicates write-protected bits. A zero is always read from these bits.
3)
"" indicates no default value has been defined.
This register is used to control interrupt event output from the /INT pin and the stop/start status of clock and
calendar operations.
1) CSEL0,1 ( Compensation interval Select 0, 1 ) bits
The combination of these two bits is used to set the temperature compensation interval.
CSEL0,1
Write/Read
2) UIE ( Update Interrupt Enable ) bit
When a time update interrupt event is generated (when the UF bit value changes from "0" to "1"), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status
remains Hi-Z).
When a "1"is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a "0"is written to this bit, no interrupt signal is generated when an interrupt event occurs.
Data
0
The VLF bit is cleared to zero to prepare for the next status detection.
1
This bit is invalid after a "1" has been written to it.
0
Data loss is not detected.
Data loss is detected. All registers must be initialized.
1
( This setting is retained until a "zero" is written to this bit. )
Data
0
The VDET bit is cleared to zero to prepare for the next low voltage detection.
1
The write access of "1" to this bit is invalid.
0
Temperature compensation is normal.
Temperature compensation is stop detected.
1
Function
bit 7
CSEL1
(Default)
(0)
CSEL1
CSEL0
(bit 7)
(bit 6)
0
0
0
1
1
0
1
1
Description
Description
bit 6
bit 5
bit 4
CSEL0
UIE
TIE
(1)
()
()
Compensation interval
0.5 s
2.0 s
Default
10 s
30 s
Page - 12
bit 3
bit 2
bit 1
AIE
()
(0)
(0)
ETM44E-01
bit 0
RESET
()
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