14.5. Oscillation stop detection function
This flag bit indicates the retained status of clock oscillation stop. Its value changes from "0" to "1" when data
loss might have occurred due to clock oscillation stop, power on resetting. Once this flag bit's value is "1", its
value is retained until a "0" is written to it.
During the initial power-on (from 0V) and/or if the value of the VLF bit is "1", be sure to initialize all registers
before using them.
14.5.1. Related registers for Oscillation stop and Voltage low detect function.
Addressh
1D
1) VLF bit
Table 31 Oscillation stop detection flag
VLF
Write
Read
14.6. FOUT function
The clock signal can be output via the FOUT pin. Output is stopped upon detection of the voltage drop below
V
In this case pin output becomes Hi-z.
DET1
14.6.1. FOUT control register.
Addressh
1C
14.6.2. FOUT function Table.
3)
FSEL1,FSEL0 bit
Table 32 FOUT Frequency selection
FSEL1
0
0
1
1
At the time of the initial power-on, "0" is set to FSEL1, FSEL0 by Power-On-Reset..
Note: The effect of STOP bit to FOUT functions.
When STOP = "1", 32.768 kHz and 1024 Hz output is possible.
But 1 Hz output is disabled.
RX8130CE
ETM50E-07
Function
bit 7
Flag Register
VBLF
Data
The VLF is cleared to 0 and waiting for next low voltage detection.
0
1
Invalid (writing 1 will be ignored)
Oscillation status is normal, RTC register data are valid.
0
Oscillation stop is detected, RTC register data are invalid.
Should be initialized of all register data.
1
VLF is maintained till it is cleared by zero.
Function
bit 7
FSEL1 FSEL0 USEL
Extension Register
FSEL0
output
0
32.768kHzOutput
1
1024HzOutput
0
1HzOutput
1
OFF
Seiko Epson Corporation
bit 6
bit 5
bit 4
bit 3
0
UF
TF
Description
bit 6
bit 5
bit 4
bit 3
TE
WADA TSEL2 TSEL1 TSEL0
14. Functions
bit 2
bit 1
bit 0
AF
RSF
VLF
VBFF
bit 2
bit 1
bit 0
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