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Texas Instruments Xilinx UG230 User Manual
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Texas Instruments Xilinx UG230 User Manual

Texas Instruments Xilinx UG230 User Manual

Starter kit board
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Spartan-3E FPGA
Starter Kit Board
User Guide
UG230 (v1.2) January 20, 2011
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Summary of Contents for Texas Instruments Xilinx UG230

  • Page 1 Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011...
  • Page 2 Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.
  • Page 3 Table of Contents Preface: About This Guide Acknowledgements ............9 Guide Contents .
  • Page 4 SMA Clock Input or Output Connector ........22 UCF Constraints .
  • Page 5 Writing Data to the Display ..........54 Disabling the Unused LCD .
  • Page 6 Related Resources ............81 Chapter 11: Intel StrataFlash Parallel NOR Flash PROM StrataFlash Connections .
  • Page 7 UCF Location Constraints ..........114 Related Resources .
  • Page 8 DDR SDRAM Series Termination and FX2 Connector Differential Termination Appendix B: Example User Constraints File (UCF) www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011...
  • Page 9 SMSC for the 10/100 Ethernet PHY • STMicroelectronics for the 16M x 1 SPI serial Flash PROM • Texas Instruments Incorporated for the three-rail TPS75003 regulator supplying most of the FPGA supply voltages • Xilinx, Inc. Configuration Solutions Division for the XCF04S Platform Flash PROM and their support for the embedded USB programmer •...
  • Page 10 Preface: About This Guide • Chapter 5, “Character LCD Screen,” describes the functionality of the character LCD screen. • Chapter 6, “VGA Display Port,” describes the functionality of the VGA port. • Chapter 7, “RS-232 Serial Ports,” describes the functionality of the RS-232 serial ports. •...
  • Page 11 Chapter 1 Introduction and Overview ® Thank you for purchasing the Xilinx Spartan -3E FPGA Starter Kit. You will find it useful in developing your Spartan-3E FPGA application. Choose the Starter Kit Board for Your Needs Depending on specific requirements, choose the Xilinx development board that best suits your needs.
  • Page 12 Chapter 10: Analog Capture Circuit Table 10-2: Programmable Gain Settings for Pre-Amplifier (Continued) Input Voltage Range Gain Minimum Maximum 1.525 1.775 1.5875 1.7125 1.625 1.675 -100 1.6375 1.6625 SPI Control Interface Figure 10-3 highlights the SPI-based communications interface with the amplifier. The gain for each amplifier is sent as an 8-bit command word, consisting of two 4-bit fields.
  • Page 13 Analog to Digital Converter (ADC) The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency. UCF Location Constraints Figure 10-5 provides the User Constraint File (UCF) constraints for the amplifier interface, including the I/O pin assignment and I/O standard used. "SPI_MOSI"...
  • Page 14 Chapter 10: Analog Capture Circuit SPI_MISO Slave: LTC1407A-1 A/D Converter AD_CONV Spartan-3E FPGA SPI_SCK Channel 1 Channel 0 Master Converted data is presented with a latency of one sample. The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV. The converted values is then presented after the next AD_CONV pulse.
  • Page 15 Disable Other Devices on the SPI Bus to Avoid Contention Disable Other Devices on the SPI Bus to Avoid Contention The SPI bus signals are shared by other devices on the board. It is vital that other devices are disabled when the FPGA communicates with the AMP or ADC to avoid bus contention.
  • Page 16 Chapter 10: Analog Capture Circuit www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011...
  • Page 17 Chapter 11 Intel StrataFlash Parallel NOR Flash PROM ® As shown in Figure 11-1, the Spartan -3E FPGA Starter Kit boards includes a 128 Mbit (16 Mbyte) Intel StrataFlash parallel NOR Flash PROM. As indicated, some of the StrataFlash connections are shared with other components on the board. Intel StrataFlash SPI Serial Flash Spartan-3E FPGA...
  • Page 18 Chapter 11: Intel StrataFlash Parallel NOR Flash PROM • Stores MicroBlaze processor code in the StrataFlash device and shadows the code into the DDR memory before executing the code. • Stores non-volatile data from the FPGA. StrataFlash Connections Table 11-1 shows the connections between the FPGA and the StrataFlash device.
  • Page 19 StrataFlash Connections Table 11-1: FPGA-to-StrataFlash Connections StrataFlash FPGA Pin Category Function Signal Name Number SF_A24 Shared with XC2C64A CPLD. The CPLD actively drives these pins during FPGA SF_A23 configuration, as described in Chapter 16, SF_A22 “XC2C64A CoolRunner-II CPLD”. Also connects to FPGA user-I/O pins. SF_A24 is the SF_A21 same as FX2 connector signal FX2_IO<32>.
  • Page 20 Chapter 11: Intel StrataFlash Parallel NOR Flash PROM Table 11-1: FPGA-to-StrataFlash Connections StrataFlash FPGA Pin Category Function Signal Name Number SF_D15 Upper 8 bits of a 16-bit halfword when SF_D14 StrataFlash is SF_D13 configured for x16 data SF_D12 (SF_BYTE=High). SF_D11 Signals SF_D<11:8>...
  • Page 21 Shared Connections Shared Connections Besides the connections to the FPGA, the StrataFlash memory shares some connections to other components. Character LCD The character LCD uses a four-bit data interface. The display data connections are also shared with the SF_D<11:8> signals on the StrataFlash PROM. As shown in Table 11-2, the FPGA controls access to the StrataFlash PROM or the character LCD using the SF_CE0 and...
  • Page 22 Chapter 11: Intel StrataFlash Parallel NOR Flash PROM UCF Location Constraints Address Figure 11-2 provides the UCF constraints for the StrataFlash address pins, including the I/O pin assignment and the I/O standard used. "SF_A<24>" = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW...
  • Page 23 Appendix A: Schematics Buttons, Switches, Rotary Encoder, and Character LCD SW0, SW1, SW2, and SW3 are slide switches. Push-button switches W, E, S, and N are located around the ROT1 push-button switch/rotary encoder. LD0 through LD7 are discrete LEDs. Chapter 2, “Switches, Buttons, and Knob,” for additional information.
  • Page 24 Buttons, Switches, Rotary Encoder, and Character LCD UG230_Aa_12_021806 Figure A-12: Schematic Sheet 13 Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com UG230 (v1.2) January 20, 2011...
  • Page 25 Appendix A: Schematics DDR SDRAM Series Termination and FX2 Connector Differential Termination Resistors R160 through R201 represent the series termination resistors for the DDR SDRAM. See Chapter 13, “DDR SDRAM,” for additional information. Resistors R202 through R210 are not loaded on the board. These landing pads provide optional connections for 100Ω...
  • Page 26 DDR SDRAM Series Termination and FX2 Connector Differential Termination UG230_Aa_13_021806 Figure A-13: Schematic Sheet 14 Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com UG230 (v1.2) January 20, 2011...
  • Page 27 Appendix A: Schematics www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011...
  • Page 28 Appendix B Example User Constraints File (UCF) ##################################################### ### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE ##################################################### # ==== Analog-to-Digital Converter (ADC) ==== some connections shared with SPI Flash, DAC, ADC, and AMP NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;...
  • Page 29 Appendix B: Example User Constraints File (UCF) NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ; NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;...
  • Page 30 NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;...
  • Page 31 Appendix B: Example User Constraints File (UCF) NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # ==== PS/2 Mouse/Keyboard Port (PS2) ==== NET "PS2_CLK"...
  • Page 32 NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ; NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ; NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ; NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ; NET "SD_UDQS"...
  • Page 33 Appendix B: Example User Constraints File (UCF) NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ; NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;...