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BKMA-7010 (Encoder/Decoder)
BKMA-7010 (Encoder/Decoder)
Video System
. Recording Part (ENC-51)
The SDI signal input from the external equipment to the
SERIAL V/A INPUT connector is converted into a parallel
signal by an SDI encoder (IC100) to produce a digital
component signal and sent through a D1 decoder (IC108)
to TBC (IC112). The resultant signal is then sent through
a VITC reader (IC203) and pre-filter (IC204) to the re-size
circuit (IC302) and re-sized to the desired horizontal pixel
size. After that, the movement of the signal is detected by
ENC3 (IC400). The signal is then converted into MPEG
image data by an encoder (IC405) and recorded on the PCI
SDRAMs (IC1401 to IC1404).
. Playback Part (DEC-109)
The image data in PCI SDRAM is input through a DMA
control circuit (IC201) to MPEG decoders (IC302 and
IC402) and decoded to a base band image signal. The two
decoders are used for selection and reproduction of the
frame precision. The video signal passed through a
selector circuit is level-controlled by a video processor
(IC603) or a blanking signal is added to the video signal.
After that, a VITC and VBI signals are added to the video
signal. Moreover, a Video index signal and EDH signals
are added to produce an SDI (serial digital interface) signal
and then output.
Audio System
. Recording Part (ENC-51)
An SDI embedded audio signal is converted by Audio
receiver (IC604) and input to the selector (IC1004).
An AES/EBU signal is decoded by a decoder (IC602) and
input to the selector.
One of these two input signals is level-controlled by a DSP
circuit (IC902) and audio-compressed by MPEG encoders
(IC700 and IC800) after it has been selected. The com-
pressed data is passed through a FIFO circuit and recorded
on PCI SDRAMs (IC1401 to IC1404).
One of the input signals described above is passed through
a FIFO circuit without compression and recorded on PCI
SDRAM when a non-compression audio signal is selected.
. Playback Part (DEC-109)
The audio data in PCI SDRAM is input through a DMA
control circuit (IC201) to MPEG audio decoders (IC703,
IC705, IC707, and IC709) and decoded to an audio signal.
The decoded signal is then level-controlled by DSP circuits
(IC802 and IC805). After that, the signal is output as an
SDI embedded signal or AES/EBU signal.
4-2 (E)
Auxiliary Data
. Recording Part (ENC-51)
The VITC data is extracted by a VITC reader (IC203).
The video index data is extracted by a pre-filter (IC204).
The VBI data is directly written in a FIFO circuit (IC501).
The three data above is written in PCI SDRAM through a
CPU bus.
. Playback Part (DEC-109)
The auxiliary data in PCI SDRAM is input through a DMA
control circuit (IC201) to a FIFO circuit (IC202). The
input signal is then added to a video signal as VITC, VBI,
and video index signals via a CPU bus.
MAV-70
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