Ethernet Interface - Arrow BeMicro CV A9 Hardware Reference Manual

B12 DDR3_DQ6
F12 DDR3_DQ7
F13 DDR3_DQ8
E14 DDR3_DQ9
J11 DDR3_DQ10
A13 DDR3_DQ11
B15 DDR3_DQ12
C15 DDR3_DQ13
G15 DDR3_DQ14
K16 DDR3_DQ15
H11 DDR3_DQS_P0
H14 DDR3_DQS_P1
G12 DDR3_DQS_N0
J13 DDR3_DQS_N1
L8 DDR3_ODT
B7 DDR3_RASn
J19 DDR3_RESETn
F7 DDR3_WEn

Ethernet Interface

The BeMicro CV A9 board includes a Micrel KSZ9021 10/100/1000 Ethernet PHY and RJ45
connector. Altera's Triple Speed Ethernet MAC soft IP core can be implemented inside the
Cyclone V FPGA to connect to the PHY through its RGMII interface.
Table 2-8: Ethernet PHY pin assignments, signal names, and functions
FPGA Pin
Schematic Signal Name
Number
M8 ENET_RX_CLK
L22 ENET_GTX_CLK
K21 ENET_RSTn
N8 ENET_INTn
K22 ENET_TX_EN
V9 ENET_RX_DV
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
Differential 1.5-V SSTL Class I Data Strobe
Differential 1.5-V SSTL Class I Data Strobe
Differential 1.5-V SSTL Class I Data Strobe
Differential 1.5-V SSTL Class I Data Strobe
1.5V SSTL Class I
1.5V SSTL Class I
LVCMOS15
1.5V SSTL Class I
I/O Standard
1
2.5 V or 3.3 V RGMII RX Clock Output from PHY
1
2.5 V or 3.3 V RGMII TX Ref Clock Input to PHY
1
2.5 V or 3.3 V Reset input to PHY
1
2.5 V or 3.3 V Interrupt Output from PHY
1
2.5 V or 3.3 V RGMII TX Control Input to PHY
1
2.5 V or 3.3 V RGMII RX Control Output from PHY
14
Data bus bit 6, byte lane 0
Data bus bit 7, byte lane 0
Data bus bit 8, byte lane 1
Data bus bit 9, byte lane 1
Data bus bit 10, byte lane 1
Data bus bit 11, byte lane 1
Data bus bit 12, byte lane 1
Data bus bit 13, byte lane 1
Data bus bit 14, byte lane 1
Data bus bit 15, byte lane 1
On Die Termination Control
Row Address Strobe
Reset in
Write Enable
Description