Arrow BeMicro CV A9 Hardware Reference Manual page 13

Table 2-7: DDR3 pin assignments, signal names, and functions
FPGA Pin Schematic Signal
Number Name
L7 DDR3_A0
K7 DDR3_A1
H8 DDR3_A2
G8 DDR3_A3
J7 DDR3_A4
J8 DDR3_A5
A10 DDR3_A6
A9 DDR3_A7
A8 DDR3_A8
A7 DDR3_A9
C6 DDR3_A10
D6 DDR3_A11
D7 DDR3_A12
C8 DDR3_A13
A5 DDR3_BA0
B10 DDR3_BA1
C9 DDR3_BA2
B6 DDR3_CASn
J9 DDR3_CLK_P
H9 DDR3_CLK_N
F14 DDR3_CKE
E9 DDR3_CSn
G11 DDR3_DM0
J17 DDR3_DM1
E12 DDR3_DQ0
D12 DDR3_DQ1
C11 DDR3_DQ2
K9 DDR3_DQ3
C13 DDR3_DQ4
D13 DDR3_DQ5
I/O Standard
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
Differential 1.5-V SSTL Class I Clock
Differential 1.5-V SSTL Class I Clock
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
1.5V SSTL Class I
13
Description
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address Bus
Bank address bus
Column address strobe
Clock Enable
Chip Select
Data Mask
Data Mask
Data bus bit 0, byte lane 0
Data bus bit 1, byte lane 0
Data bus bit 2, byte lane 0
Data bus bit 3, byte lane 0
Data bus bit 4, byte lane 0
Data bus bit 5, byte lane 0