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A3M36SL039
Airfast Power Amplifier Module with Autobias Control
Rev. 0 — December 2021
The A3M36SL039 is a fully integrated Doherty power amplifier module
designed for wireless infrastructure applications that demand high
performance in the smallest footprint. Ideal for applications in massive MIMO
systems, outdoor small cells and low power remote radio heads. The field-
proven LDMOS power amplifiers are designed for TDD and FDD LTE
systems. The module integrates an autobias feature with the option to
overwrite production settings. Autobias automatically sets and regulates
transistor bias over temperature upon power up. An integrated sensor for
monitoring temperature is also present. Communications to the module can
be accomplished via either I
3400–3800 MHz
Typical LTE Performance: P
Input Signal PAR = 8 dB @ 0.01% Probability on CCDF.
Carrier Center
Frequency
3410 MHz
3600 MHz
3790 MHz
1. All data measured with device soldered in NXP reference circuit.
Features
• Advanced high performance in-package Doherty
• Fully matched (50 ohm input/output, DC blocked)
• Designed for low complexity analog or digital linearization systems
• Autobias on power up
• Temperature sensing
C or SPI)
• Digital interface (I
2
• Embedded registers and DACs for setting bias conditions
• Tx Enable control pin for TDD operation
NXP reserves the right to change the detail specifications as may be required to permit improvements
in the design of its products.
2
C or SPI.
= 8 W Avg., V
= 29 Vdc, 1 × 20 MHz LTE,
out
DD
Gain
ACPR
(dB)
(dBc)
29.5
–28.6
29.8
–30.9
29.4
–29.1
1
PAE
(%)
36.7
38.3
36.4
Data Sheet: Technical Data
A3M36SL039I
A3M36SL039S
3400–3800 MHz, 29 dB,
8 W Avg. Airfast Power
Amplifier Module with
Autobias Control
10 mm × 8 mm Module
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Summary of Contents for NXP Semiconductors A3M36SL039I
- Page 1 Data Sheet: Technical Data The A3M36SL039 is a fully integrated Doherty power amplifier module designed for wireless infrastructure applications that demand high A3M36SL039I performance in the smallest footprint. Ideal for applications in massive MIMO A3M36SL039S systems, outdoor small cells and low power remote radio heads. The field- proven LDMOS power amplifiers are designed for TDD and FDD LTE systems.
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Page 2: Table Of Contents
Contents Pinout configuration and function ....3 Component layout and parts list ....14 Pin connections ..........3 Component layout ......... 14 Functional pin description ........ 4 Component designations and values .... 15 Electrical characteristics ........4 Temperature sensor ........15 Ratings ............ -
Page 3: Pinout Configuration And Function
Pinout configuration and function Pinout configuration and function 1.1 Pin connections Figure 1. Pin connections A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021 3 / 33 Data Sheet: Technical Data... -
Page 4: Functional Pin Description
Electrical characteristics 1.2 Functional pin description Table 1. Functional pin description Pin Number Pin Function Pin Description Carrier Drain Supply, Stage 2 Carrier Drain Supply, Stage 1 3, 5, 6, 8, 14, 17, 22, 23, 25, 26, 27, 28, 29, Ground 30, 31, 32, 33, 34, 35, 36, 37, 38 4, 18, 21... -
Page 5: Lifetime
Electrical characteristics 2.1.2 Lifetime Table 3. Lifetime Characteristic Symbol Value Unit Mean Time to Failure MTTF >10 Years Case Temperature 125°C, Internal Sense Temperature 108°C, 8 W Avg., 75% Duty Cycle, 30 Vdc 2.1.3 ESD protection characteristics Table 4. Lifetime ESD protection characteristics Test Methodology Class Human Body Model (per JS-001-2017) -
Page 6: Functional Tests
Electrical characteristics 2.2.2 Functional tests Table 7. Functional tests Characteristic Symbol Unit Functional Tests — 3400 MHz (In NXP Doherty Production ATE Test Fixture, 50 ohm system) V = 29 Vdc, Nominal DAC Settings, Tx_EN = High, P = 8 W Avg., 1-tone CW, f = 3400 MHz. Gain 26.7 29.1... -
Page 7: Register Map And Otp Memory
Register map and OTP memory Register map and OTP memory 3.1 One-time programmable memory The A3M36SL039 contains a one-time programmable (OTP) memory array that is used to store register values for the integrated autobias controller. The data sheet I target values are determined and programmed into the OTP memory during NXP’s production testing. - Page 8 Register map and OTP memory Table 10. Register map Register Definition Address Register Register Default (in Decimal) Attribute Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Value System_Reg Soft Refresh Chip Version [3:0] (Read 8'b0000_0001 Reset only) A_Sense_DAC Reserved Group A Sense DAC OTP value COPY...
- Page 9 Register map and OTP memory Table 11. Register overview and bit description Power Register On/Reset Overwritten Address Name Bit Descriptions Value by OTP Attribute Mode System_Reg Not available Soft Reset. A 1 written to this register will perform a reset of all registers to their default values.
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Page 10: Power Supply Sequence
Power supply sequence Table 11. Register overview and bit description (continued) Power Register On/Reset Overwritten Address Name Bit Descriptions Value by OTP Attribute Mode B_Sense_DAC 6–7 Not available Sense DAC B 6-bit logic value for 0–5 6'h20 peaking amplifiers. DAC B sets the reference voltage to compare to the across the reference device. -
Page 11: Autobias Functionality
Autobias functionality Power Down Sequence power down SPI/I C interface deactivated _+5V: 5 V power down Note: All digital interfaces (SDA, SCLK, CS_B,Tx_EN) are 1.8 V logic. Autobias functionality 5.1 General overview After power up, the integrated bias controller develops and applies a thermally compensated quiescent bias voltage to the gate of each of the four RF transistors contained within the power amplifier module (PAM) based on the preset OTP values. -
Page 12: Tx Enable Control
Autobias functionality Figure 2. Block diagram of carrier (A) autobias functionality. Peaking (B) autobias functionality is identical. The initial bias condition is set via the A_Sense_DAC register. The bias condition is then sensed and adjusted as temperature changes via the closed-loop feedback. The feedback mechanism adjusts the DAC ceiling voltage to maintain a constant I current through the reference FET. -
Page 13: Vgs_Dac
Ordering information 5.5 VGS_DAC The VGS_DAC voltage is determined via the Sense_DAC setting, creating the top end or ceiling of the VGS_DAC voltage range and a fixed offset voltage creating the bottom end or floor of the VGS_DAC voltage range. With a decimal VGS_DAC setting of 0, the gate voltage developed on the reference FET is buffered with minimum offset to the gates of the RF transistors in the carrier amplifier. -
Page 14: Component Layout And Parts List
Component layout and parts list Component layout and parts list 7.1 Component layout Figure 3. A3M36SL039 reference circuit component layout A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021 14 / 33 Data Sheet: Technical Data... -
Page 15: Component Designations And Values
Temperature sensor 7.2 Component designations and values Table 14. A3M36SL039 reference circuit component designations and values Part Description Part Number Manufacturer 30 Ω Ferrite Bead BLM15PD300SN1 Murata C1, C2, C14, C15 10 µF Chip Capacitor GRM31CR61H106KA12 Murata C4, C10, C12 1 µF Chip Capacitor GRM188R61H105KAAL Murata... -
Page 16: Communication Interfaces
The preferred interface type must be set at the factory prior to shipment. For I C functionality, order part number A3M36SL039I. For SPI functionality, order part number A3M36SL039S. 9.1 SPI The A3M36SL039S can be programmed and the Tx bias settings and temperature read through the 3-pin SPI interface. -
Page 17: I 2 C Addressing
• MSB sent first, LSB last 9.2 I The A3M36SL039I follows the I C protocol standard. It supports I C fast mode with a bit rate up to 400 Kbit/s. It also supports C standard mode with bit rate up to 100 Kbit/s. -
Page 18: I 2 C Instruction Set
Communication interfaces 9.2.2 I C instruction set C Write instruction Figure 7. I C Write instruction C Read instruction Figure 8. I C Read instruction A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021 18 / 33 Data Sheet: Technical Data... -
Page 19: I 2 C Device Id Read Instruction
Communication interfaces C Write and Read combination sequence Figure 9. I C Write and Read combination sequence 9.2.3 I C Device ID Read instruction The Device ID is read only, hardwired in the device and can be accessed as follows: START condition The leader sends the Reserved Device ID I C bus address followed by the R/W bit set to ‘0’... -
Page 20: I 2 C Electrical Specification And Timing For I/O Stages And Bus Lines
Communication interfaces Table 18. I C Device Read instructions Leader to Leader to Leader to Leader to Leader to Follower to Leader to Leader to Follower Follower Follower Follower Follower Leader Follower Follower START 1111 1000 XXXXXXX+‘0/1’ RESTART 1111 1001 3 bytes ID NACK STOP... -
Page 21: I 2 C Sclk And Sda Characteristics
Communication interfaces 9.3.1 I C SCLK and SDA characteristics Table 19. I C SCLK and SDA Symbol Parameter Conditions Unit SCLK clock frequency — SCLK After this period, the first clock Hold time (repeated) START condition — µs HD;STA pulse is generated. Low period of the SCLK clock —... -
Page 22: I 2 C Bus Electrical Characteristics
Design considerations 9.3.2 I C bus electrical characteristics Table 20. I C SCLK and SDA Symbol Parameter Conditions Unit LOW-level input voltage — — 0.3*V HIGH-level input voltage — 0.7*V — Hysteresis of Schmitt trigger inputs — 0.05*V — (Open-drain/open-collector) at LOW-level output voltage 0.2*V 2 mA sink current V... -
Page 23: Programming Guidelines To Avoid Hardware Failure Or Damage
Design considerations 10.2 Programming guidelines to avoid hardware failure or damage Users must be aware of the following guidelines to avoid potential hardware failure or damage. • Do not program the Refresh OTP and Soft Reset bits to a 1 state at the same time. •... - Page 24 Design considerations CS_B<7:0> CS_B<0> CS_B<1> CS_B<2> CS_B<3> CS_B<7> A3M36SL039 A3M36SL039 A3M36SL039 A3M36SL039 A3M36SL039 <0> <1> <2> <3> <7> SCLK CS_B<15:8> CS_B<8> CS_B<9> CS_B<10> CS_B<11> CS_B<15> A3M36SL039 A3M36SL039 A3M36SL039 A3M36SL039 A3M36SL039 <8> <9> <10> <11> <15> Controller SCLK CS_B<63:56> CS_B<56> CS_B<57> CS_B<58>...
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Page 25: Product Marking
Product marking 11 Product marking Figure 13. Product marking A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021 25 / 33 Data Sheet: Technical Data... -
Page 26: Package Information
Package information 12 Package information Figure 14. Package information A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021 26 / 33 Data Sheet: Technical Data... - Page 27 Package information Figure 14. Package information A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021 27 / 33 Data Sheet: Technical Data...
- Page 28 Package information Figure 14. Package information A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021 28 / 33 Data Sheet: Technical Data...
- Page 29 Package information Figure 14. Package information A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021 29 / 33 Data Sheet: Technical Data...
- Page 30 Package information Figure 14. Package information A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021 30 / 33 Data Sheet: Technical Data...
- Page 31 Package information Figure 14. Package information A3M36SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, December 2021 31 / 33 Data Sheet: Technical Data...
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Page 32: Product Software And Tools
Revision history 13 Product software and tools Refer to the following resources to aid your design process. Development Software • Test, Debug and Analyzer Software Development Tools • Printed Circuit Boards 14 Failure analysis At this time, because of the physical characteristics of the part, failure analysis is limited to electrical signature analysis. In cases where NXP is contractually obligated to perform failure analysis (FA) services, full FA may be performed by third party vendors with moderate success. - Page 33 How to Reach Us Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses Home Page: granted hereunder to design or fabricate any integrated circuits based on the information nxp.com in this document.
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