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3.3.9
MIPI-CSI2 Connector
CSI Camera Connector
Pin
Signal
Pin
Signal
1
MIPI_CSI0_D3_N
10
MIPI_CSI0_D0_N
2
MIPI_CSI0_D3_P
11
MIPI_CSI0_D0_P
3
MIPI_CSI0_D2_N
12
GND
4
MIPI_CSI0_D2_P
13
MIPI_CSI0_EN
5
MIPI_CSI0_D1_N
14
MIPI_CSI0_MCLK_OUT
6
MIPI_CSI0_D1_P
15
MIPI_CSI0_I2C0_SCL
7
MIPI_CSI0_CLK_N 16
MIPI_CSI0_I2C0_SDA
8
MIPI_CSI0_CLK_P
17
MIPI_CSI0_RST_B
9
GND
18
+3V3_RUN
EMI compliance requirements.
MIPI_CSI0_I2C0_SCL: I2C Bus clock line, Output signal, electrical level +1V8_RUN
MIPI_CSI0_I2C0_SDA: I2C Bus data line. Bidirectional signal, electrical level +1V8_RUN
MIPI_CSI0_RST_B: External camera module reset signal output, it is an active low signal.
When connecting CSI cameras to CN8 connector, it is strongly recommended to use shielded cable for EMC compatibility.
SBC-C57
SBC-C57 User Manual - Rev. First Edition: 1.0 - Author: S.O. - Reviewed by R.Z. - Copyright © 2021 SECO S.p.A.
The i.MX8X family of processors includes a MIPI-CSI2, 4-lanes, camera input which
CN8
can be accessed on the SBC-C57 through a FFC/FPC connector, type HIROSE
p/n FH12-18S-0.5SH(55) which is able to accept 18 poles 0.5mm pitch FFC
cables.
MIPI_CSI_D0_P / MIPI_CSI_D0_N: MIPI CSI Port differential data pair #0.
MIPI_CSI0_D1_P / MIPI_CSI0_D1_N: MIPI CSI Port differential data pair #1.
MIPI_CSI0_D2_P / MIPI_CSI0_D2_N: MIPI CSI Port differential data pair #2.
MIPI_CSI0_D3_P / MIPI_CSI0_D3_N: MIPI CSI Port differential data pair #3.
MIPI_CSI0_CLK_P / MIPI_CSI0_CLK_N: MIPI CSI Port differential clock pair.
MIPI_CSI_EN: External camera module Power down signal. It is an active high signal with electrical level
+1.8V_RUN
MIPI_CSI0_MCKL_OUT: Master Clock, electrical level +1V8_RUN. It is suggested to use camera
modules with onboard crystal / oscillator and avoid using this signal. Indeed, it could cause problems for
-up resistor.
-up resistor.
29
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