1. Manuals
  2. Brands
  3. Artesyn Embedded Technology Manuals
  4. Computer Hardware
  5. SharpStreamer Mini PCIE-7205
  6. Installation and user

Artesyn Embedded Technology SharpStreamer Mini PCIE-7205 Installation And User

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
P R E L I M I N A R Y V E R S I O N
SharpStreamer™ Mini PCIE-7205
Installation and Use
P/N: 6806800U01A
April 2016

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SharpStreamer Mini PCIE-7205 and is the answer not in the manual?

Questions and answers

Related Manuals for Artesyn Embedded Technology SharpStreamer Mini PCIE-7205

Summary of Contents for Artesyn Embedded Technology SharpStreamer Mini PCIE-7205

  • Page 1 P R E L I M I N A R Y V E R S I O N SharpStreamer™ Mini PCIE-7205 Installation and Use P/N: 6806800U01A April 2016...
  • Page 2 © Copyright 2016 Artesyn Embedded Technologies, Inc. All rights reserved. Trademarks Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc. All other names and logos referred to are trade names, trademarks, or registered trademarks of their respective owners.

  • Page 3: Table Of Contents

    Contents Contents About this Manual ............... 11 Safety Notes .
  • Page 4 Contents Contents Contents CPLD ................41 3.3.1 Programming the CPLD .
  • Page 5 Contents BIOS ................67 Connecting to the Console .
  • Page 6 Contents Contents Contents 6.3.3.2 Connect to a PCIE-7205 CPU using amtterm ......96 Software Upgrade ..............97 Software Removal .
  • Page 7 List of Tables Table 1-1 Standard Compliances ............27 Table 1-2 Ordering Information .
  • Page 8 List of Tables SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)
  • Page 9 List of Figures Figure 1-1 Mechanical Layout ............25 Figure 3-1 PCIE-7205 Block Diagram .
  • Page 10 List of Figures SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)

  • Page 11: About This Manual

    About this Manual Overview of Contents This manual is divided into the following chapters and appendices. Safety Notes on page 15 provides information about the safety regulations that should be  observed while operating the product. Sicherheitshinweise on page 19 provides information about German translation of the ...
  • Page 12 About this Manual About this Manual Abbreviations This document uses the following abbreviations: Abbreviation Definition Active Management Technology CPLD Complex Programmable Logic Device DHCP Dynamic Host Configuration Protocol Field Replaceable Unit GPIO General Purpose Input Output Internet Service Provider JTAG Joint Test Action Group Media Access Control Multi-Chip Package...
  • Page 13 About this Manual Conventions The following table describes the conventions used throughout this manual. Notation Description 0x00000000 Typical notation for hexadecimal numbers (digits are 0 through F), for example used for addresses and offsets 0b0000 Same for binary numbers (digits are 0 and 1) bold Used to emphasize a word Used for on-screen output and code related elements...
  • Page 14 About this Manual About this Manual Notation Description Indicates a hazardous situation which, if not avoided, could result in death or serious injury. Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message. No danger encountered.

  • Page 15: Safety Notes

    Safety Notes This section provides warnings that precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed during all phases of operation, service, and repair of this equipment. You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment.
  • Page 16 Safety Notes Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. Changes or modifications not expressly approved by Artesyn Embedded Technologies could void the user's authority to operate the equipment.
  • Page 17 Safety Notes Installation Damage of Circuits Electrostatic discharge and incorrect installation and removal of the product can damage circuits or shorten their life. Before touching the product or electronic components, make sure that your are working in an ESD-safe environment. Product Damage Incorrect installation of the product can cause damage of the product.
  • Page 18 Safety Notes SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)

  • Page 19: Sicherheitshinweise

    Sicherheitshinweise Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind.
  • Page 20 Sicherheitshinweise Das Produkt wurde in einem Artesyn Standardsystem getestet. Es erfüllt die für digitale Geräte der Klasse A gültigen Grenzwerte in einem solchen System gemäß den FCC-Richtlinien Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen angemessenen Schutz vor Störstrahlung beim Betrieb des Produktes in Gewerbe- sowie Industriegebieten gewährleisten.
  • Page 21 Sicherheitshinweise Überhitzung und Beschädigung des Produktes Betreiben Sie das Produkt ohne Zwangsbelüftung, kann das Produkt überhitzt und schließlich beschädigt werden. Bevor Sie das Produkt betreiben, müssen Sie sicher stellen, dass das Gerät über eine Zwangskühlung verfügt. Fehlerhafter Datenbestand Wenn sie die Spannungsversorgung des Produkts abschalten, während Programmdaten im Flashspeicher aktualisiert, werden, können diese Daten nicht korrekt gespeichert werden.
  • Page 22 Sicherheitshinweise SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)

  • Page 23: Introduction

    Chapter 1 Introduction This chapter describes overview of SharpStreamer™ Mini PCIE-7205 card, applications, features, hardware overview, software overview, standard compliance, and ordering information. The Artesyn SharpStreamer™ Mini PCIE-7205 is designed as a high-density server media accelerator card that enables service provider networks to offer video transcoding services quickly and dynamically.

  • Page 24: Hardware Overview

    Introduction 8GB of DDR3 1600 memory on each processor/accelerator.  Two Micro SD card slots up to 32 GB for each processor/accelerator.  10G Ethernet interface per CPU to support video encoder application.  Optimized H.264/AVC and H.265/HEVC transcoding density in a smaller format. ...

  • Page 25: Software Overview

    Introduction The dimensions of the PCIE-7205 card are 167.65 mm x 106.65mm. See, Figure 1-1 for more details. Figure 1-1 Mechanical Layout 167.65 mm Software Overview 1.3.1 Host OS The recommended host OS is a standard 64-Bit CentOS 7.x desktop linux distribution. The PCIE-7205 was tested on the host system running with CentOS 7.1.

  • Page 26: Pci7207 Utility

    Introduction On the host system, for each PCIE-7205 card installed, the host detects two (2) Gigabit ethernet interfaces; each of these ethernet interfaces is associated with one PCIE-7205 CPU. The PCIE-7205 ethernet interfaces on the host provide access only to the PCIE-7205 CPUs. Note: The PCIE-7205 shares the pci7207 utility and PCIE-7207 OS.

  • Page 27: Standard Compliances

    Introduction Standard Compliances The PCIE-7205 card meets the following standards. Table 1-1 Standard Compliances Standard Description EN55022: 2011 Class A CISPR 22: 2012 Radiated Emissions EN 300 386 V1.6.1: 2012 Class A EN 55022: 2011 FCC 15.109(b): 2015 Class A ANSI C63.4: 2003 FCC 15.109(g) (CISPR 22:1997): 2003 Class A ANSI C63.4: 2003 ICES-003 (Issue 5): 2012 Class A CAN/CSA-CISPR 22: 2008...
  • Page 28 Introduction Table 1-2 Ordering Information Part Number Description ® PCIE-7205-2-2 PCIE card with 2x dual-core Intel Core™ i5-5350U Processor 1.8 GHz, ® 2x Intel 82599EN 10G Ethernet controllers connected to front panel SFP+ sockets SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)

  • Page 29: Hardware Preparation And Installation

    Chapter 2 Hardware Preparation and Installation This chapter provides information on unpacking and inspecting the card procedure, safety precautions. The environmental, thermal, and power requirements, and the installation and removal procedures of the card are explained in this chapter. Unpacking and Inspecting PCIE-7205 Card Damage of Circuits Electrostatic discharge and incorrect installation and removal of the card can damage circuits or shorten their life.

  • Page 30: Environmental, Thermal, And Power Requirements

    Hardware Preparation and Installation 3. Remove the desiccant bag shipped with the card and dispose it according to your country’s legislation. Make sure the card is thoroughly inspected before shipment. If any damage has occurred during transportation please contact our Contact Center immediately. Environmental, Thermal, and Power Requirements This section contains the environmental, thermal, and power requirements of the PCIE-7205...

  • Page 31: Table 2-1 Environmental And Thermal Requirements

    Hardware Preparation and Installation The following table provides the environmental and the thermal requirements for the PCIE- 7205 card. Table 2-1 Environmental and Thermal Requirements Requirement Operating Non-Operating Temperature 0°C to 50°C -40°C to 70°C Minimum Airflow 500 LFM (2.5 m/sec) (Reference to sea level) 400 LFM (2 m/sec) for 35°C Operation...

  • Page 32: Power Requirements

    Hardware Preparation and Installation 2.2.2 Power Requirements Before installing the card, make sure that the system is capable of delivering the required power. The following table provides the typical power consumed by the PCIE-7205 card. Table 2-2 Power Requirements Mode PCIe slot power Idle 8W (+/- 10%)
  • Page 33 Hardware Preparation and Installation Electrostatic Discharge Do not touch the circuit board with bare hands. The static electricity of the human body may damage the ElectroStatic Sensitive Devices (ESSDs) on the circuit board. Make sure that you wear an ElectroStatic Discharge (ESD) preventive wrist strap or antistatic glove to prevent the static electricity from hurting you or damaging the device.

  • Page 34: Esd Prevention

    Hardware Preparation and Installation 2.3.1 ESD Prevention Static electricity may hurt you or damage the device. To minimize the damage, pay attention to the following points: Before touching the card or electronic components, make sure that you are working in an ...

  • Page 35: Pcie-7205 Card Installation And Removal

    Hardware Preparation and Installation Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life. Before touching the module or electronic components, make sure that you are working in an ESD safe environment. PCIE-7205 Card Installation and Removal This section contains the PCIE-7205 card installation and removal procedures.

  • Page 36: Pcie-7205 Card Installation

    Hardware Preparation and Installation 2.4.1 PCIE-7205 Card Installation To install the PCIE-7205 card, perform the following steps: 1. Use anti-static pads and attach an ESD strap to your wrist. Attach the other end of the ESD strap to an electrical ground (For more details, refer to the section Precautions on page 32).

  • Page 37: Pcie-7205 Card Removal

    Hardware Preparation and Installation 2.4.2 PCIE-7205 Card Removal To remove the PCIE-7205 card, perform the following steps: 1. Make sure you are in an ESD-safe environment. 2. Power off the system, disconnect the system from the electrical outlet and peripherals and remove any cables connected to the card.
  • Page 38 Hardware Preparation and Installation SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)

  • Page 39: Functional Description

    Chapter 3 Functional Description This chapter describes the functional blocks of the PCIE-7205 card, processor features, CPU block, MCP block, and power management. The Gigabit ethernet, temperature sensors, I2C bus support are also explained in this chapter. The PCIe 7205 card is designed as a server accelerator contains two Intel® Core™ processor subsystems (dual core with Hyperthreading).With two cores and two threads per core for a total of 8 additional threads running at 2.2Ghz.

  • Page 40: Figure 3-1 Pcie-7205 Block Diagram

    Functional Description Figure 3-1 PCIE-7205 Block Diagram PCIe Gen2 x4 Not POR for 20 Gbps final product DDR3L DDR3L Intel 82599EN DDR3L DDR3L DDR3L DDR3L Face Plate DDR3L Memory DDR3L DDR3L DDR3L Memory Memory Memory DDR3L 10GbE (SFI) 10Gbps SFI DDR3L Memory Memory...

  • Page 41: Intel I350 Ethernet Controller

    Functional Description Intel i350 Ethernet Controller The Intel i350 is the main interface between the Server PCIe bus and the Target Media Accelerator Processors. The PCIE-7205 card utilizes the i350-AM2 variant which has a x4 PCIe Gen 2 bus going to the Gold Fingers of the PCIe edge card. The other side of the i350 are two Gigabit Ethernet Buses, each Gigabit Ethernet link goes to one MCP accelerator.

  • Page 42: Cpld Operation

    Functional Description Programming the CPLD can be accomplished in either of two ways: through the empty P8 header on the component side of the board, or through the gold fingers of the PCIe connector.This method can also be used to update the CPLD. Currently there is no method to program the CPLD through either linux or other software.

  • Page 43: Intel I5-5350U Broadwell Processor

    Functional Description 3.4.1 Intel i5-5350U Broadwell Processor The Broadwell processor is the intended processor for the production of PCIE-7205 card. 3.4.2 Clock Distribution Clocking for each MCP complex consists of two crystals. One 24 Mhz crystal to drive all the main buses and a 32.768 Khz crystal to drive the real time clock.

  • Page 44: Gigabit Ethernet

    Functional Description Figure 3-2 Reset Architecture Reset Diagram CPU Complex (x2) DRAM Devices 3.3V_ATX 3.3V_ATX Broadwell-U CPLD R E S E T_N R E S E T_N R E S E T_N R E S E T_N R E S E T_N R E S E T_N R E S E T_N SM_DRAMRST#...

  • Page 45: Gigabit Ethernet

    Functional Description 3.4.5 10 Gigabit Ethernet Each MCP is connected to an Intel 82599EN Single 10 Gigabit Ethernet Controller. The controller is connected to the CPU via x4 PCIe link. The 10GbE controller is configured to support 10G SFI to be connected to a SFP+ connector on the rear panel. This interface will enable video encoder application.
  • Page 46 Functional Description The following figure shows the location of the MicroSD cards and the corresponding MCPs on the board. Figure 3-3 MCP Location SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)

  • Page 47: Microsd As Firmware Recovery Option

    Functional Description Figure 3-4 MicroSD Card Location 3.4.7.1 MicroSD as Firmware Recovery Option The MicroSD can be used as a BIOS recovery option. Format the MicroSD card as fat32, then copy the recovery firmware onto the card. Insert the card into the socket, and install the card into the server.

  • Page 48: Microsd As Non-Volatile Storage

    Functional Description 3.4.7.2 MicroSD as Non-Volatile Storage The MicroSD slots can accommodate up to 32GB of flash storage that can be used as storage, similar to a flash thumb drive. 3.4.7.3 MicroSD as Boot Device By default, during the board boot operation, the BIOS will first look for a boot record on the MicroSD storage device.

  • Page 49: Figure 3-5 Location Of Temperature Sensors Primary Side

    Functional Description Figure 3-5 Location of Temperature Sensors Primary Side U128 Temperature U120 Temperature P P RIMARY SIDE U80 Temperature U45 Temperature SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)

  • Page 50: Voltage And Current Monitor

    Functional Description Figure 3-6 Location of Temperature Sensors Secondary Side S S ECONDARY SIDE U43 Temperature U37 Temperature 3.4.9 Voltage and Current Monitor There is a voltage and current monitor on the bulk 12 V bus to the MCP core voltage regulator for each MCP.

  • Page 51: Power

    Functional Description Power The maximum power budget of PCIE-7205 is up to 70W only. The power supply for this card is provided by two power rails,12 V and 3.3 V from host, through PCIe Gold Finger connector. For PCIE7205, this two power rails are now connected via single resistor so that all power shall be supplied by the PCIe Gold finger.
  • Page 52 Functional Description SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)

  • Page 53: Controls, Indicators, And Connectors

    Chapter 4 Controls, Indicators, and Connectors This chapter contains information about the controls, indicators, and connectors associated with the PCIE-7205 card. Connectors The pinout descriptions of the key connectors on the PCIE-7205 card are provided in this section. 4.1.1 Edge Connector This section provides information about the PCIE-7205 card Edge Connector (Gold Finger) pinout.
  • Page 54 Controls, Indicators, and Connectors Table 4-1 PCIE-7205 Card Edge Connector Pinout (continued) Pin # Name Side B Description Name Side A Description WAKE# Signal for Link reactivation PERST# PCIe Edge PERST_L Main PCIe reset from the host system Mechanical Key PCIE PCIE EDGE CLKREQ LOW;...

  • Page 55: Leds

    Controls, Indicators, and Connectors Table 4-1 PCIE-7205 Card Edge Connector Pinout (continued) Pin # Name Side B Description Name Side A Description Ground PERp2 PCIE1 EDGE RX P PCIE1 EDGE RX N Ground PERn2 Receiver Lane 2, Differential pair PETp3 PCIE3 EDGE TX P Ground PCIE3 EDGE TX N...

  • Page 56: Figure 4-1 Led Arrangement View

    Controls, Indicators, and Connectors Figure 4-1 LED Arrangement View The following table contains information about the LEDs on the PCIE-7205 card. Table 4-2 PCIE-7205 LEDs Label # Color Status Description Debug LEDs Green1 ON = MCP1 out of reset. OFF = MCP1 in reset. BLINKING = Server is holding MCP1 power off through i350 GPIO see “pci7205”...
  • Page 57 Controls, Indicators, and Connectors Table 4-2 PCIE-7205 LEDs (continued) Label # Color Status Description Red1 Power fail decoder bit 0 Red2 Power fail decoder bit 1 Red3 Power fail decoder bit 2 Red4 Power fail decoder bit 3 Amber1 Solid amber MCP1 CATERR# BLINKING amber MCP1 THERMTRIP# Amber2 ON: MCP1 PCPH_PG &&...
  • Page 58 Controls, Indicators, and Connectors Table 4-2 PCIE-7205 LEDs (continued) Label # Color Status Description CATERR#: Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors.

  • Page 59: Controls

    Controls, Indicators, and Connectors Controls A Reset button SW2 is available at the rear side of the PCIE-7205 card. By pressing the Reset button (labeled as SW2), all the MCP processors on the card get reset. The following figure shows the Reset button location on the card. Figure 4-2 Reset Button Location Reset...

  • Page 60: P8 Cpld Programmer Pinout

    Controls, Indicators, and Connectors The P7 switch control drives to GPIO inputs on the CPLD and is intended for future development.The P7 switch control when ON, will isolate the CPLD Programming Header away from the JTAG chain to be able to program the CPLD Table 4-3 Pinout for P7 GPIO Switches Name 3.3V Pull up...

  • Page 61: Ports

    Controls, Indicators, and Connectors Table 4-4 CPLD Programming Pinout Name CPLD TDI 3.3V CPLD TD0 Ports This section provides information about ports on the PCIE-7205 card. 4.5.1 SFP + Port PCIE7205 provide two SFP+ ports in the rear panel . Table 4-5 SFP+ Connector Pinout (J1 and J2) Name Name...

  • Page 62: Debug Port

    Controls, Indicators, and Connectors 4.5.2 Debug Port PCIE7205 implement a mezzanine board to fan out several ports for display, debug and programming. Each MCP has one debug port, for PCIE7205 total of two debug ports. Table 4-6 Debug Port (P2, P11) Name Name Name...

  • Page 63: Debug Board Ports

    Controls, Indicators, and Connectors Table 4-6 Debug Port (P2, P11) (continued) Name Name Name Display Port Display Port AUX XDP JTAG TRST Data 1+ USB Port 2 Serial UART CTS MCP System DATA - Power OK Display Port XDP JTAG TDI Data 1 - SPI Prog Chip Serial UART...

  • Page 64: Microusb Port

    Controls, Indicators, and Connectors Table 4-7 Micro Display Port Pinout (J3 and J4) (continued) Name Name Lane1 + Lane3 + VCC 1.5 A fused 3.3 V 4.5.3.2 MicroUSB Port The MicroUSB port is the USB port of the PCH which is also commonly known as the debug port from Intel.

  • Page 65: Serial Port

    Controls, Indicators, and Connectors Table 4-9 Debug XDP Port Pinout (J17 and J18) (continued) Name Name Name VCCIO OUT PRDY_l Power Debug # PLTRST # XDP SYSTEM POWER OK DBR # JTAG TDO JTAG TRST JTAG TDI CFG3 JTAG TCK JTAG TMS Power Good 4.5.3.4...

  • Page 66: Spi Fw Programming Port

    Controls, Indicators, and Connectors Table 4-10 Serial Port (P5 & P6) Name Request To Send Clear To Send 4.5.3.5 SPI FW Programming Port The SPI header can be used with a dediprog sf100 to program or read the SPI flash for each MCP complex.

  • Page 67: Bios

    Chapter 5 BIOS This chapter describes about BIOS setup, serial port configuration parameters, steps to access the BIOS setup screen, and configuring the BIOS settings. The Basic Input Output System (BIOS) acts as an interface between the operating system and the hardware of the card.

  • Page 68: Accessing The Bios Setup Screen

    BIOS Accessing the BIOS Setup Screen When the system is turned on or rebooted, the presence and functionality of the system components is tested by POST (Power-On Self Test). For more information on how to connect to the console PCIE-7205, refer the section Access a PCIE-7205 CPU via AMT on page The menus shown in the figures in this chapter are from a typical system.
  • Page 69 BIOS Select Save and Exit after making a selection in the setup menus. This procedure stores the selections displayed in the menus in CMOS. At the time of next boot up, BIOS configures the system according to the setup selection stored in CMOS. For more details, refer to the section Exit Menu on page 87.

  • Page 70: Menu Bar

    BIOS 1. Press <F2> to return to the BIOS setup. 2. Go to the Exit menu and select Load setup Defaults.The default BIOS values are loaded and the values will affect all setup items and also the previously altered reset options. The default values set become effective only after saving and exiting the BIOS setup.

  • Page 71: Legend Bar

    BIOS 5.2.2 Legend Bar The keys listed in the legend bar below on the BIOS Setup Screen screen are used to make selections on screen or to move out of the current menu. The legend keys and their alternate options are explained in Table 5-3.

  • Page 72: Field Help

    BIOS 5.2.3 Field Help The help text of the selected field is displayed on the right side of the screen. By scrolling through each field, the related help text of the active selection is displayed. 5.2.4 General Help You can press <F1>on the keyboard in any menu context to invoke the general help window. The general help window describes the legend keys and their alternates as shown in the following figure.

  • Page 73: Configuring Bios Setup Settings

    BIOS Configuring BIOS Setup Settings This section provides BIOS configuration in each of the menu options. 5.3.1 Main Menu To view the Main menu, select the Main tab from the menu bar. By default, the Main tab is selected on the BIOS Setup screen. To modify menu screen items, scroll down the Main screen.

  • Page 74: Advanced Menu

    BIOS The following table provides the list of features that can be configured in Main menu and their default values. Table 5-4 Main Menu Selection Options/Format Description Language English/French/Chinese/Japanese Set the setup language System Time HH:MM:SS Set the system time System Date MM/DD/YYYY Set the system date...

  • Page 75: Boot Configuration

    BIOS Use the legend keys to make a selection or exit in/from the Advanced menu. The following table provides a brief description about the list of configurations that can be performed in the Advanced menu. Table 5-5 Advanced Menu Feature Description Boot Configuration Select the boot configuration...

  • Page 76: Table 5-6 Boot Configuration

    BIOS The following table provides information about options in the Boot Configuration submenu and their default values. The values shown in the tables enclosed within brackets [...] indicate the default settings. Table 5-6 Boot Configuration Feature Options Description Numlock [On] Enables or disables Numlock SharpStreamer™...

  • Page 77: Console Redirection Setup

    BIOS 5.3.2.2 Console Redirection Setup The following figure shows the Console Redirection Setup submenu screen. The settings are applied to all ports, if selected. Individual submenus are available, if there is a need for separate port configuration. Figure 5-6 Console Redirection Setup The following table provides information about the feature options in the Console Redirection Setup submenu and their defaults values.
  • Page 78 BIOS Table 5-7 Console Redirection Setup (continued) Feature Option Description Terminal Type [VT_100] Selects the terminal type VT_100+ VT_UTF8 PC_ANSI Baud Rate [115200] Selects the baud rate 57600 38400 19200 9600 4800 2400 1200 Data Bits 7 Bits Selects the data bits [8 Bits] Parity [none]...
  • Page 79 BIOS Table 5-7 Console Redirection Setup (continued) Feature Option Description Text Mode Resolution AUTO Selects the text mode resolution [Force 80x25] Force 80x24 (DEL FIRST ROW) Force 80x24 (DEL LAST ROW) AutoRefresh Disabled Selects if the terminal will be refreshed after a console is detected [Enabled] FailSafeBaudRate...

  • Page 80: Serial Io Configuration

    BIOS 5.3.2.3 Serial IO Configuration The following figure shows the Serial IO Configuration submenu. This menu is necessary to enable the UART0 serial port for debug purposes. Figure 5-7 Serial IO Configuration The following table provides information about Serial IO Configuration submenu options and their default settings.

  • Page 81: Security Menu

    BIOS 5.3.3 Security Menu To view the Security menu, select Security tab from the menu bar. Use the legend keys to make a selection and exit from the Security menu. The Security menu appears as shown in the following figure. Figure 5-8 Security Menu The following table provides other options in the Security menu and their defaults.

  • Page 82: Power Menu

    BIOS Table 5-9 Security Menu Feature Option Description Set Supervisor Password Sets the password 5.3.4 Power Menu To view the Power menu, select the Power tab from the menu bar. The Power menu is displayed which looks similar to the following figure. Figure 5-9 Power Menu The following table provides other options in the Power menu and their defaults.

  • Page 83: Advanced Cpu Control

    BIOS 5.3.4.1 Advanced CPU Control The following figure shows the Advanced CPU Control submenu. Figure 5-10 Advanced CPU Control The following table provides options in the Advanced CPU Control submenu and their defaults. Table 5-11 Advanced CPU Control Feature Options Description HT Support [Auto]...
  • Page 84 BIOS Table 5-11 Advanced CPU Control (continued) Feature Options Description Intel (VMX) Virtualization [Enabled] Enables or disables the CPU Technology virtualization support Disabled Boot Performance Mode Max Non-Turbo Performance Selects the performance state the BIOS left behind Max Battery before entering the OS [Turbo Performance] Turbo Mode Disabled...

  • Page 85: Boot Menu

    BIOS 5.3.5 Boot Menu To view the Boot menu, select Boot tab on the menu bar. The Boot menu screen is displayed as shown below. Figure 5-11 Boot Menu The following table provides options in the Boot menu and their default settings. Table 5-12 Boot Menu Feature Option...
  • Page 86 BIOS Table 5-12 Boot Menu (continued) Feature Option Description Network Stack Disabled Enables or disables UEFI and Legacy network support [Enabled] PXE Boot capability Disabled Enables or disables the alternate PXE boot modes UEFI:IPv4 UEFI:IPv6 UEFI:IPv4/IPv6 [Legacy] Add Boot Options First Selects the position of an added boot device Last...

  • Page 87: Exit Menu

    BIOS 5.3.6 Exit Menu To view the Exit menu, select Exit tab from the menu bar. Use the legend keys to make a selection or exit to the main menu. The Exit menu screen looks similar to the figure below. Figure 5-12 Exit Menu The following table provides Exit menu features and their description.

  • Page 88: Updating The Bios

    BIOS Updating the BIOS The PCIE-7205 OS includes a utility to perform BIOS updates. Two different forms of BIOS updates are supported. BIOS region only update: This is the recommended update mechanism.  Full BIOS update: This updates the BIOS and Intel ME regions. A provisioning of AMT is ...

  • Page 89: Software Installation

    Chapter 6 Software Installation In order to control, configure, and interact with the PCIE-7205 card installed in the host system you need to install the core OS and required applications on top of the host system. This chapter provides information on how to prepare a host system and also the prerequisites required for installing PCIE-7205 OS and pci7207 utility.

  • Page 90: Firewall Configuration

    Software Installation  tftp-server  syslinux To install the above listed packages on the host system: 1. Log in to the host system as root 2. Run the following commands. yum install epel-release yum install dhcp yum install tftp-server yum install syslinux 6.1.1.1 Firewall Configuration The CentOS 7.1 installation has the Firewall service enabled by default.

  • Page 91: Pci7207 Utility Installation

    Software Installation To enable TFTP server: 1. Log in to the host as root. 2. Run the following commands. cd / ln –s /var/lib/tftpboot /tftpboot 3. Modify the file /etc/xinetd.d/tftp with the editor. 4. Change disabled = yes to disabled = no, save the file and exit. 5.

  • Page 92: Dhcp Configuration

    Software Installation 6.1.1.5 DHCP Configuration The PCIE-7205 CPUs will obtain their IP addresses from the host system via DHCP. For this process to work, it is necessary to create a DHCP configuration file and to initialize the host Ethernet interfaces associated with the PCIE-7205 cards in the host system. 1.

  • Page 93: Pcie-7205 Os Installation

    Software Installation PCIE-7205 OS Installation To install the PCIE-7205 OS: 1. Copy the PCIE-7205 OS image to the host system. Obtain the latest version of the PCIE-7205 OS image using the SWORDS download server available from the Artesyn Customer Resource Center Website (http://crcportal.artesyn.com).

  • Page 94: Network Interfaces

    Software Installation 6.3.1 Network Interfaces The pci7207 utility used to initialize the network interfaces creates an internal network with separate subnets for each PCIE-7205 Ethernet interface. The pci7207 utility finds all the PCIE- 7205 cards in the system and assigns them a CARD ID to each one based on their PCI bus. It then uses the CARD ID and CPU number to create the separate subnets as, 172.20.<card id><cpu>.1 for the PCIE-7205 Host Ethernet interface, and 172.20.<card id><cpu>.100 for the corresponding PCIE-7205 CPU Ethernet interface.

  • Page 95: Access A Pcie-7205 Cpu Via Amt

    Software Installation 6.3.3 Access a PCIE-7205 CPU via AMT The PCIE-7205 CPUs have the AMT network enabled. The CPU console can be accessed via VNC or SOL. The AMT password is “P@ssw0rd” for all CPUs. The following are VNC viewers which have been verified to work with the PCIE-7205: RealVNC ...

  • Page 96: Connect To A Pcie-7205 Cpu Using Amtterm

    Software Installation cd amtterm-1.3 cp amtterm amttool /usr/local/bin cd /root rm –rf tmp The best way to install amtterm in a CentOS 7.1 host is to get the CentOS 6.5 amtterm and then install it using yum to get all the dependencies installed as well. 6.3.3.2 Connect to a PCIE-7205 CPU using amtterm To view a PCIE-7205 CPU serial console using AMT SOL:...

  • Page 97: Software Upgrade

    Software Installation pcie7207 login: root Password: Last login: Thu Jan 30 09:29:08 on ttyS0 [root@pcie7207 ~]# Only one AMT connection is allowed per MCP. AMT does not support multiple AMT connections to a single Host. Software Upgrade To upgrade the host OS software, follow the CentOS 7.x documentation. To upgrade the pci7207 utility, obtain the new version of the utility using the SWORDS download server available from the Artesyn Customer Resource Center Website and follow the installation procedure outlined in the section...
  • Page 98 Software Installation 4. Remove the pcie7205start startup script. chkconfig --del pcie7205start rm /etc/init.d/pcie7205start SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)

  • Page 99: Utilities And Applications

    Chapter 7 Utilities and Applications The PCIE-7205card comes with the tool pci7207 utility. This chapter provides more information about pci7205 utility and its usage. In addition to that the PCIE-7205 OS related information such as sensor information, BIOS update and AMT provisioning is explained in this chapter.

  • Page 100: Pci7205 Usage

    Utilities and Applications 7.1.1 pci7205 Usage The following section contains the list of commands in pci7205 utility. Display utility help  # pci7207 -h Usage: pci7207 options Options: Display version Display help Backwards compatibility -s ID PCIE-7205 card id 1-24 -n CPU CPU 1 - 4 -c CMD...
  • Page 101 Utilities and Applications # pci7207 -b -cl CARD SIZE CPU MAC INTF 01:00.0 0xf7800000 0x100000 ec:9e:cd:15:d7:8c enp1s0f0 01:00.1 0xf7700000 0x100000 ec:9e:cd:15:d7:8d enp1s0f1 02:00.0 0xf7300000 0x100000 ec:9e:cd:15:e9:c9 enp2s0f0 02:00.1 0xf7200000 0x100000 ec:9e:cd:15:e9:ca enp2s0f1 List PCIE-7205 cards installed in the system.  # pci7207 -cl CARD CPU SIZE...
  • Page 102 Utilities and Applications host enp1s0f1_cpu2 { hardware ethernet ec:9e:cd:14:d4:5e; fixed-address 172.20.12.100; } subnet 172.20.21.0 netmask 255.255.255.0 { option broadcast-address 172.20.21.255; next-server 172.20.21.1; host enp2s0f0_cpu1 { hardware ethernet ec:9e:cd:15:e9:c9; fixed-address 172.20.21.100; } subnet 172.20.22.0 netmask 255.255.255.0 { option broadcast-address 172.20.22.255; next-server 172.20.22.1; host enp2s0f1_cpu2 { hardware ethernet ec:9e:cd:15:e9:ca;...
  • Page 103 Utilities and Applications – Power Cycle all 4 CPUs in a PCIE-7205 # pci7207 -s1 –cp – Power Cycle all CPUs in all PCIE-7205s in the system # pci7207 –cp Execute BIOS Crisis Recovery for a PCIE-7205 CPU.  Executing a BIOS Crisis Recovery for a PCIE-7205 CPU requires a MicroSD card to be inserted in the MicroSD slot for the PCIE-7205 CPU.

  • Page 104: Pcie-7205 Os

    Utilities and Applications PCIE-7205 OS 7.2.1 Sensor Information The PCIE-7205 OS has a utility to display sensor information locally on each CPU. 1. Log in to the host system as root 2. Log in to a PCIE-7205 CPU as root 3.

  • Page 105: Amt Provisioning

    Utilities and Applications scp pcie7205_<BIOS release>_signed.fd 172.20.11.100:/root amtterm –pP@ssw0rd 172.20.11.100 cd /opt/InsydeBios ./H2OFFTx64.sh /root/pcie7205_<BIOS release>_signed.fd –BIOS The procedure takes a few minutes. A CPU power cycle might be required after completion of the BIOS update. To perform a full BIOS update on a PCIE-7205 CPU: 1.
  • Page 106 Utilities and Applications SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)

  • Page 107: Related Documentation

    3. In the Search text box, type the product name and click GO. Table A-1 Artesyn Embedded Technologies - Embedded Computing Publications Document Title Publication Number SharpStreamer Mini PCIE-7205 Quick Start Guide 6806800U02 SharpStreamer Mini PCIE-7205 Safety Notes Summary 6806800U03...
  • Page 108 Related Documentation SharpStreamer™ Mini PCIE-7205 Installation and Use (6806800U01A)
  • Page 110 Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc. All other product or service names are the property of their respective owners. © 2016 Artesyn Embedded Technologies, Inc.

Table of Contents