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Artesyn Embedded Technology SharpStreamer Pro PCIE-7210 Installation And Use Manual

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SharpStreamer™ Pro PCIE-7210
Installation and Use
P/N: 6806800U29D
September 2017

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Summary of Contents for Artesyn Embedded Technology SharpStreamer Pro PCIE-7210

  • Page 1 SharpStreamer™ Pro PCIE-7210 Installation and Use P/N: 6806800U29D September 2017...
  • Page 2 © Copyright 2017 Artesyn Embedded Technologies, Inc. All rights reserved. Trademarks Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc. All other names and logos referred to are trade names, trademarks, or registered trademarks ©...

  • Page 3: Table Of Contents

    Contents About this Manual ............... 13 Safety Notes .
  • Page 4 Contents 3.5.1 High Speed IO subsystem ........... . . 42 3.5.2 Low Speed Serial Interface .
  • Page 5 Contents 5.2.2.2 Console Redirection Setup ......... . . 80 5.2.3 Security Menu .
  • Page 6 Contents 7.3.2 CPLD Upgrade ............. . 115 Boardcontrol .
  • Page 7 Contents MaxCore Firmware Upgrade ............131 MaxCore Firmware Upgrade .
  • Page 8 Contents SharpStreamer™ Pro PCIE-7210 Installation and Use ( 6806800U29D)
  • Page 9 List of Tables Table 1-1 Standard Compliances ............28 Table 1-2 Ordering Information .
  • Page 10 List of Tables SharpStreamer™ Pro PCIE-7210 Installation and Use ( 6806800U29D)
  • Page 11 List of Figures Figure 1-1 Mechanical Layout ............27 Figure 3-1 SharpStreamer™...
  • Page 12 List of Figures SharpStreamer™ Pro PCIE-7210 Installation and Use ( 6806800U29D)

  • Page 13: About This Manual

    About this Manual Overview of Contents This manual is divided into the following chapters and appendices. Safety Notes on page 17 provides information about the safety regulations that should be  observed while operating the product. Sicherheitshinweise on page 21 provides information about German translation of the ...
  • Page 14 About this Manual About this Manual Abbreviations This document uses the following abbreviations: Abbreviation Definition CPLD Complex Programmable Logic Device DHCP Dynamic Host Configuration Protocol DIMM Per Channel Field Replaceable Unit GPIO General Purpose Input Output HEVC High Efficiency Video Coding Internet Service Provider JTAG Joint Test Action Group...
  • Page 15 About this Manual Conventions The following table describes the conventions used throughout this manual. Notation Description 0x00000000 Typical notation for hexadecimal numbers (digits are 0 through F), for example used for addresses and offsets 0b0000 Same for binary numbers (digits are 0 and 1) bold Used to emphasize a word Used for on-screen output and code related elements...
  • Page 16 About this Manual About this Manual Notation Description Indicates a hazardous situation which, if not avoided, could result in death or serious injury. Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message. No danger encountered.

  • Page 17: Safety Notes

    Safety Notes This section provides warnings that precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed during all phases of operation, service, and repair of this equipment. You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment.
  • Page 18 Safety Notes Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. Changes or modifications not expressly approved by Artesyn Embedded Technologies could void the user's authority to operate the equipment.
  • Page 19 Safety Notes Installation Damage of Circuits Electrostatic discharge and incorrect installation and removal of the product can damage circuits or shorten their life. Before touching the product or electronic components, make sure that your are working in an ESD-safe environment. Product Damage Incorrect installation of the product can cause damage of the product.
  • Page 20 Safety Notes SharpStreamer™ Pro PCIE-7210 Installation and Use ( 6806800U29D)

  • Page 21: Sicherheitshinweise

    Sicherheitshinweise Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind.
  • Page 22 Sicherheitshinweise Das Produkt wurde in einem Artesyn Standardsystem getestet. Es erfüllt die für digitale Geräte der Klasse A gültigen Grenzwerte in einem solchen System gemäß den FCC-Richtlinien Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen angemessenen Schutz vor Störstrahlung beim Betrieb des Produktes in Gewerbe- sowie Industriegebieten gewährleisten.
  • Page 23 Sicherheitshinweise Überhitzung und Beschädigung des Produktes Betreiben Sie das Produkt ohne Zwangsbelüftung, kann das Produkt überhitzt und schließlich beschädigt werden. Bevor Sie das Produkt betreiben, müssen Sie sicher stellen, dass das Gerät über eine Zwangskühlung verfügt. Fehlerhafter Datenbestand Wenn sie die Spannungsversorgung des Produkts abschalten, während Programmdaten im Flashspeicher aktualisiert, werden, können diese Daten nicht korrekt gespeichert werden.
  • Page 24 Sicherheitshinweise SharpStreamer™ Pro PCIE-7210 Installation and Use ( 6806800U29D)

  • Page 25: Introduction

    PCI Express card footprints that are easily deployable in off-the-shelf platforms. Each SharpStreamer Pro PCIE-7210 CPU is capable of up to eight (8) streams of 1080p30 H.265/High Efficiency Video Coding (HEVC) transcodes, or four (4) streams of 1080p60 H.265/HEVC transcodes.

  • Page 26: Hardware Overview

    Introduction Two DDR4 SODIMM modules connected to each Intel® Xeon® Processor E3-1578L v5  each with 8GB memory. Two uSD card slots supporting up to 32GB, one for each processor.  Two USB 2.0 ports on faceplate one from each processor. ...

  • Page 27: Software Overview

    Introduction Figure 1-1 Mechanical Layout 312 mm R453 C546 C677 C422 R484 C405 R499 C676 C429 C304 R489 R794 R488 C397 C671 C169 C399 C174 C391 C542 R498 C534 R496 C528 C393 C536 C394 R490 C446 C190 C490 C165 R238 C338 C662 C333...

  • Page 28: Standard Compliances

    Introduction Standard Compliances The PCIE-7210 card meets the following standards. Table 1-1 Standard Compliances Standard Description EN55022: 2011 Class A CISPR 22: 2012 Radiated Emissions EN 300 386 V1.6.1: 2012 Class A EN 55022: 2011 FCC 15.109(b): 2015 Class A ANSI C63.4: 2003 FCC 15.109(g) (CISPR 22:1997): 2003 Class A ANSI C63.4: 2003 ICES-003 (Issue 5): 2012 Class A CAN/CSA-CISPR 22: 2008...

  • Page 29: Ordering And Support Information

    Introduction Ordering and Support Information Use the part number given in the following table, when ordering a card, supported software packages, or requesting support information. Consult your local Artesyn sales representative for more information. Table 1-2 Ordering Information Part Number Description PCIE-7210-2 PCIE card with two Quad Core Intel®...
  • Page 30 Introduction SharpStreamer™ Pro PCIE-7210 Installation and Use ( 6806800U29D)

  • Page 31: Hardware Preparation And Installation

    Chapter 2 Hardware Preparation and Installation This chapter provides information on unpacking and inspecting the card procedures and safety precautions to be followed while handling the card. The environmental, thermal, and power requirements, and the installation and removal procedures of the card are also explained in this chapter.

  • Page 32: Environmental, Thermal, And Power Requirements

    Hardware Preparation and Installation 3. Remove the desiccant bag shipped with the card and dispose it according to your country’s legislation. Make sure the card is thoroughly inspected before shipment. If any damage has occurred during transportation please contact our Contact Center immediately. Environmental, Thermal, and Power Requirements This section contains the environmental, thermal, and power requirements of the PCIE-7210...

  • Page 33: Power Requirements

    Hardware Preparation and Installation The following table provides the environmental and the thermal requirements for the PCIE- 7210 card. Table 2-1 Environmental and Thermal Requirements Requirement Operating Non-Operating Temperature 0°C to 35°C -40°C to 70°C Minimum Airflow 500 LFM (2.5 m/sec) (Reference to sea level) 400 LFM (2 m/sec) for 35°C Operation...

  • Page 34: Precautions

    Hardware Preparation and Installation Precautions To reduce the risk of personal injury, fire, or damage to the equipment, do not  overload the AC supply circuit that provides power to the chassis. The card must be powered and connected only to a controlled voltage source. ...

  • Page 35: Esd Prevention

    Hardware Preparation and Installation 2.3.1 ESD Prevention Static electricity may hurt you or damage the device. To minimize the damage, pay attention to the following points: Before touching the card or electronic components, make sure that you are working in an ...

  • Page 36: Pcie-7210 Card Installation And Removal

    Hardware Preparation and Installation PCIE-7210 Card Installation and Removal This section contains the PCIE-7210 card installation and removal procedures. Shipping the card along with a server is not recommended. If you still need to ship the card along with the server, ensure the card is properly secured in the server.

  • Page 37: Pcie-7210 Card Removal

    Hardware Preparation and Installation 4. Insert the PCIE-7210 card into the PCIe slot, secure it, and ensure that the card is properly fitted in the PCIe slot. 5. Lock the slot ejectors, close the system cover and then power on the system. Make sure that the card has enough air flow after closing the system with the cover.
  • Page 38 Hardware Preparation and Installation 4. Remove the screw holding the front panel bracket and gently pull the PCIE-7210 card from the slot. Place the PCIE-7210 card into an ESD-protective bag and seal it appropriately. 5. Close the cover of the system. SharpStreamer™...

  • Page 39: Functional Description

    Chapter 3 Functional Description This chapter describes the functional blocks of the SharpStreamer™ Pro PCIE-7210 card. The PCIE-7210 server accelerator card provides the processor subsystem for the Artesyn MaxCore system. The PCIE-7210 comes in a PCI Express like form factor with MaxCore-specific modifications and extensions.

  • Page 40: Intel Skylake Processor

    Functional Description 3.1.1 Intel Skylake Processor Skylake is an Intel core-2015 platform. It is 64 bit, multi core processor built on 14nm process technology. The H-processor line is offered in a 2-Chip Platform and is connected to a discrete PCH chip on the motherboard. It is a BGA1440 Package supporting the GT2 and GT4 Graphics Configuration.

  • Page 41: Ddr4 2133 Memory

    Functional Description DDR4 2133 Memory The PCIE-7210 card comes with four DDR4 SODIMM channels, two on each E3-1578L v5 processor. Each DIMM is populated with 8GB of memory. That means, each processor has an 16GB DDR4 memory (8GB on each channel) running at DDR4-2133 speed, resulting a total 32GB of memory on each PCIE-7210 card.

  • Page 42: Interface Mechanism

    Functional Description Interface Mechanism 3.5.1 High Speed IO subsystem The following are the list of High speed I/O peripherals on the card: PCIe  – x8 PCIe lanes are connected between standard PCIe card edge connector and each E3-1578L v5 processor. Each lane operates at Gen 3 (8 GT/s). –...

  • Page 43: Low Speed Serial Interface

    Functional Description  One GE port is connected between each PCH and the Edge connector 2 through i219 and i347 devices. 3.5.2 Low Speed Serial Interface 3.5.2.1 Two-wire interface  The SML is System management logic. SML is a low speed connection for low power state mode for manageability communication.

  • Page 44: Micro Sd Card

    Functional Description Micro SD card There are two microSD slots available on each PCIE-7210 card. Each microSD card goes to one of the respective PCH (J2 for PCH1 and J8 for PCH2). The microSD card slot is designed either for a non- volatile storage space, and/or as a Firmware recovery option. The microSD cards need to be inserted into their slots before power is applied to the card.

  • Page 45: Microsd As Firmware Recovery Option

    Functional Description 3.6.1 MicroSD as Firmware Recovery Option The microSD can be used as a BIOS recovery option. For this you need to perform the following steps: 1. Format the microSD card as FAT32, then copy the recovery firmware onto the card. 2.

  • Page 46: Clock Distribution

    Functional Description Figure 3-3 shows the location of the temperature sensors on the card. Figure 3-3 Location of Temperature Sensors - Secondary Side U91 Temperature sensor U68 Temperature sensor R582 C430 R972 C1767 R785 R1229 R1228 C1286 C1271 C1309 C1307 R577 R447 C1268...

  • Page 47: 3.10 Jtag

    Functional Description 3.10 JTAG The PCIe slot JTAG pins are mapped to the CPLD JTAG programming pins. CPLD programming port at connector P2 (Independent connector for CPLD)  E3-1578L v5 and PCH JTAG pins are connected to XDP connector  SharpStreamer™...
  • Page 48 Functional Description SharpStreamer™ Pro PCIE-7210 Installation and Use ( 6806800U29D)

  • Page 49: Controls, Indicators, And Connectors

    Chapter 4 Controls, Indicators, and Connectors This chapter contains information about the controls, indicators, and connectors associated with the PCIE-7210 card. Connectors 4.1.1 PCIE-7210 Faceplate View The following figure shows the faceplate view of PCIE-7210 card. Figure 4-1 PCIE-7210 Faceplate Push Button Reset CPU1 Push Button...

  • Page 50: Edge Connector 1

    Controls, Indicators, and Connectors The PCIE-7210 card comes with two gold finger edge connectors referred as Edge Connector 1 and Edge Connector 2. 4.1.2 Edge Connector 1 This section provides information about the PCIE-7210 card Edge Connector 1 (Gold Finger) pinout.
  • Page 51 Controls, Indicators, and Connectors Table 4-1 PCIE-7210 Card Edge Connector 1 Pinout (continued) Pin # Name Side B Description Name Side A Description Tx_N(0) Differential pair Ground Ground Rx_P(0) Receiver Lane 0 PRSNT2# Hot-Plug presence detect Rx_N(0) Differential pair Ground Ground Tx_P(1) Transmitter Lane 1...
  • Page 52 Controls, Indicators, and Connectors Table 4-1 PCIE-7210 Card Edge Connector 1 Pinout (continued) Pin # Name Side B Description Name Side A Description Tx_P(6) Transmitter Lane 6 Ground Tx_N(6) Differential pair Ground Ground Rx_P(6) Receiver Lane 6 Ground Rx_N(6) Differential pair Tx_P(7) Transmitter Lane 7 Ground...

  • Page 53: Edge Connector 2

    Controls, Indicators, and Connectors Table 4-1 PCIE-7210 Card Edge Connector 1 Pinout (continued) Pin # Name Side B Description Name Side A Description Tx_N(12) Differential pair Ground Ground Rx_P(12) Receiver Lane 12 Ground Rx_N(12) Differential pair Tx_P(13) Transmitter Lane 13 Ground Tx_N(13) Differential pair...
  • Page 54 Controls, Indicators, and Connectors Table 4-2 PCIE-7210 Card Edge Connector 2 Pinout (continued) Pin # Name Side B Description Name Side A Description +12V +12 Volt power +12V +12 Volt power +12V +12 Volt power +12V +12 Volt power +12V +12 Volt power +12V +12 Volt power...
  • Page 55 Controls, Indicators, and Connectors Table 4-2 PCIE-7210 Card Edge Connector 2 Pinout (continued) Pin # Name Side B Description Name Side A Description Ground PCH1_USB Differential pair 2_BMC_D PCH2_GE Gigabit Ethernet port to Ground 0_EXT_R PCH2 Receiver (Diff pair) X_D_P PCH2_GE Ground 0_EXT_R...
  • Page 56 Controls, Indicators, and Connectors Table 4-2 PCIE-7210 Card Edge Connector 2 Pinout (continued) Pin # Name Side B Description Name Side A Description Ground PCH1_100 Reference Clock to PCH1 M_REFCLK_ Ground PCH1_100 Differential pair M_REFCLK_ Not connected Ground Not connected Not connected Not connected Not connected...
  • Page 57 Controls, Indicators, and Connectors Table 4-2 PCIE-7210 Card Edge Connector 2 Pinout (continued) Pin # Name Side B Description Name Side A Description PCH1_LP LPC Port to PCH1 bus Ground C_LAD0 PCH1_LP PCH1_LPC_ LPC Frame to PCH1 C_LAD1 LFRAME_N PCH1_LP PCH1_SERI LPC Interrupt signal C_LAD2...
  • Page 58 Controls, Indicators, and Connectors Table 4-2 PCIE-7210 Card Edge Connector 2 Pinout (continued) Pin # Name Side B Description Name Side A Description PCH2_SA SATA1 Port to PCH2 Ground TA1_RX_ Receiver (Diff pair) PCH2_SA Ground TA1_RX_ Ground PCH2_SATA SATA1 port to PCH2 1_TX_D_P Transmitter (Diff pair Ground...
  • Page 59 Controls, Indicators, and Connectors Table 4-2 PCIE-7210 Card Edge Connector 2 Pinout (continued) Pin # Name Side B Description Name Side A Description PCH1_SA SATA1 port to PCH1 Ground TA1_RX_ Receiver (Diff pair) PCH1_SA Ground TA1_RX_ Ground PCH1_SATA SATA1 port to PCH1 1_TX_D_P Transmitter (Diff pair) Ground...

  • Page 60: Micro Usb Uart Port

    Controls, Indicators, and Connectors 4.1.4 Micro USB UART Port The micro USB-UART port is the UART0 port of the PCH through CP2105-F01-GMR silabs device. Table 4-3 Micro USB-UART port pinout Name VBUS Data- Data+ Identification 4.1.5 MicroUSB Port The micro USB port is the USB 1 port of the PCH. Table 4-4 Micro USB port pinout Name VCC 5V...

  • Page 61: Leds

    Controls, Indicators, and Connectors LEDs The following figure shows the general usage LEDs D17, D15, D13, D14, D16, D14, D12, and D10. Figure 4-2 General Usage LEDs R972 C1767 R582 C430 R785 R1229 R1228 C1286 C1309 C1307 R577 R447 C1268 R1227 R1499 C1271...
  • Page 62 Controls, Indicators, and Connectors Table 4-5 Sleep Signal Status (continued) Representation V alue Status Green LINK/ACTIVITY (Asserted steady when link is established and there is no transmit or receive activity. Blinking when there is link and receive or Transmit activity.) Green LINK/ACTIVITY (Asserted steady when link is...

  • Page 63: Table 4-6 Cpu1 And Cpu2 Nic 82599 Leds

    Controls, Indicators, and Connectors The following figure shows the CPU1 and CPU2 NIC 82599 LEDs D40, D44, D36, and D32. Figure 4-4 Location of CPU1 and CPU2 NIC 82599 LEDs R582 C430 R972 C1767 R785 R1229 R1228 C1286 C1309 C1307 R577 R447 C1268...

  • Page 64: Figure 4-5 Location Of Cpu1 I219 Leds

    Controls, Indicators, and Connectors Table 4-6 CPU1 and CPU2 NIC 82599 LEDs (continued) Label # Color Status Description Green Port 0 CPU2 - LINK/ACTIVITY (Asserted steady when link is established and there is no transmit or receive activity. Blinking when there is link and receive or Transmit activity.) Green Port 1 CPU2 - LINK/ACTIVITY (Asserted steady when link...

  • Page 65: Figure 4-6 Location Of Cpu2 I219 Leds

    Controls, Indicators, and Connectors Table 4-7 CPU1 i219 LEDs (continued) Label # Color Status Description Green i219 Default - Link Up/Activity (200 ms on/200 ms off) Green iI219 Default - Link 1000 Green i219 Default - Link 100 The following figure shows the CPU2 i219 LEDs D47, D48, and D49. Figure 4-6 Location of CPU2 i219 LEDs R972...

  • Page 66: Figure 4-7 Location Of Cpu1 Usb2240 Leds

    Controls, Indicators, and Connectors Table 4-8 CPU2 i219 LEDs (continued) Label # Color Status Description Green i219 Default - Link 1000 Green i219 Default - Link 100 The following figure shows the CPU1 USB2240 LED D3. Figure 4-7 Location of CPU1 USB2240 LEDs R582 C430 R972 C1767...

  • Page 67: Table 4-9 Cpu1 And Cpu2 Usb2240 Leds

    Controls, Indicators, and Connectors The following figure shows the CPU1 USB2240 LED D18. Figure 4-8 Location of CPU2 USB2240 LEDs R582 C430 R972 C1767 R785 R447 R1229 R1228 R1227 C1286 C1271 C1309 C1307 R577 C1268 R1499 C647 R788 C1284 R443 C582 C1292 C1305...

  • Page 68: Controls

    Controls, Indicators, and Connectors Controls A reset button is available at the rear side of the PCIE-7210 card. By pressing the reset button (labeled as S1), CPLD on the card get reset. The following figure shows the reset button location on the PCIE-7210 card. Figure 4-9 Reset Button S1 Location CPLD Reset - (S1)

  • Page 69: Figure 4-10 Reset Button S2 And S3 Location

    Controls, Indicators, and Connectors Figure 4-10 Reset Button S2 and S3 Location CPU1 Reset (S3) CPU2 Reset (S2) R453 C546 C677 C422 C405 R484 R499 C676 C429 C304 R489 R794 R488 C397 C671 C169 C391 C399 C174 C542 R498 C534 R496 C528 C536...
  • Page 70 Controls, Indicators, and Connectors SharpStreamer™ Pro PCIE-7210 Installation and Use ( 6806800U29D)

  • Page 71: Bios

    Chapter 5 BIOS This chapter describes about BIOS setup, serial port configuration parameters, steps to access the BIOS setup screen, and configuring the BIOS settings. The Basic Input Output System (BIOS) acts as an interface between the operating system and the hardware of the card.
  • Page 72 BIOS To access BIOS Setup screen, press <F2> when the message Press <F2> to enter BIOS setup appears on the screen. The following figure depicts a sample BIOS Setup screen. Figure 5-1 BIOS Setup Screen BIOS Setup screen Menu Bar Legend Bar Select Save and Exit after making a selection in the setup menus.
  • Page 73 BIOS In order to navigate setup, use the arrow keys on the key to highlight items on the menu. All other navigation possibilities are shown at the bottom of the menu. Additionally, an item- specific help is displayed on the right hand side of the menu window. It displays the help text for the currently selected field.

  • Page 74: Menu Bar

    BIOS 5.1.1 Menu Bar Table 5-1 provides information about the BIOS Setup screen menu bar options. Table 5-1 BIOS Setup Menu Bar Menu Description Main Configuring the basic system. Advanced Setting the advanced features available on the system chipset. Security Setting the security password.

  • Page 75: Field Help

    BIOS To display a submenu, use the arrow keys to move the cursor to the desired submenu and then press <Enter>. Table 5-2 Legend Keys Function Displays general help window. Exits the menu or the BIOS Setup program without saving any changes.

  • Page 76: General Help

    BIOS 5.1.4 General Help You can press <F1>on the key in any menu context to invoke the general help window. The general help window describes the legend keys and their alternates as shown in the following figure. The scroll bar on the right side of any window indicates that there is more than one page of information in the window.

  • Page 77: Main Menu

    BIOS 5.2.1 Main Menu To view the Main menu, select the Main tab from the menu bar. By default, the Main tab is selected on the BIOS Setup screen. To modify menu screen items, scroll down the Main screen. The following screen appears. Figure 5-3 Main Menu The following table provides the list of features that can be configured in Main menu.

  • Page 78: Advanced Menu

    BIOS Table 5-3 Main Menu Selection Options/Format Description System Time HH:MM:SS Set the system time System Date MM/DD/YYYY Set the system date 5.2.2 Advanced Menu To view Advanced menu, select Advanced tab from the menu bar. Figure 5-4 Advanced Menu Use the legend keys to make a selection or exit in/from the Advanced menu.

  • Page 79: Boot Configuration

    BIOS The following table provides the frequently configurable settings in the Advanced menu. The other configurations shown in the Advanced menu are default values and need not be configured. Table 5-4 Advanced Menu Feature Description Boot Configuration To select the boot configuration. Console Redirection To change console redirection parameter.

  • Page 80: Console Redirection Setup

    BIOS The following table provides information about options in the Boot Configuration submenu and their default values. The values shown in the tables enclosed within brackets [...] indicate the default settings. Table 5-5 Boot Configuration Feature Options Description Numlock [On] Enables or disables Numlock.

  • Page 81: Table 5-6 Console Redirection Setup

    BIOS The following table provides information about the feature options in the Console Redirection Setup submenu and their defaults values. Table 5-6 Console Redirection Setup Feature Option Description Console Serial [Enabled] Enables or disables the Console Redirection Redirection. Disabled Terminal Type [VT_100] Selects the terminal type.
  • Page 82 BIOS Table 5-6 Console Redirection Setup (continued) Feature Option Description Information Wait Time 0 Second Selects the information screen display time. 2 Second [5 Second] 10 Second 30 Second C.R. After Post [Yes] Selects if the Console Redirections is enabled after Post. Text Mode Resolution AUTO Selects the text mode resolution.

  • Page 83: Security Menu

    BIOS 5.2.3 Security Menu To view the Security menu, select Security tab from the menu bar. Use the legend keys to make a selection and exit from the Security menu. The Security menu appears as shown in the following figure. Figure 5-7 Security Menu The following table provides other options in the Security menu and their defaults.

  • Page 84: Power Menu

    BIOS Table 5-7 Security Menu Feature Option Description Set Supervisor Password Sets the password 5.2.4 Power Menu To view the Power menu, select the Power tab from the menu bar. The Power menu is displayed which looks similar to the following figure. Figure 5-8 Power Menu SharpStreamer™...

  • Page 85: Boot Menu

    BIOS 5.2.5 Boot Menu To view the Boot menu, select Boot tab on the menu bar. The Boot menu screen is displayed as shown below. Figure 5-9 Boot Menu The following table provides options in the Boot menu and their default settings. Table 5-8 Boot Menu Feature Option...
  • Page 86 BIOS Table 5-8 Boot Menu (continued) Feature Option Description Network Stack [Disabled] Enables or disables UEFI and Legacy network support Enabled PXE Boot capability [Disabled] Enables or disables the alternate PXE boot modes UEFI:IPv4 UEFI:IPv6 UEFI:IPv4/IPv6 Legacy Power Up In Standby [Disabled] Support Add Boot Options...

  • Page 87: Exit Menu

    BIOS The values shown in the tables enclosed within brackets [...] indicate the default settings. 5.2.6 Exit Menu To view the Exit menu, select Exit tab from the menu bar. Use the legend keys to make a selection or exit to the main menu. The Exit menu screen looks similar to the figure below. Figure 5-10 Exit Menu The following table provides Exit menu features and their description.

  • Page 88: Bios Boot Parameter

    BIOS Table 5-9 Exit Menu (continued) Feature Description Save Changes Without Exit Saves the changes without exiting Exit Discarding Changes Exits the setup and discards the changes Load Setup Defaults Loads the default setup parameter Discard Changes Discards all changes performed BIOS Boot Parameter The BIOS reads the boot parameters from CPLD's shared memory and interprets the parameters for various purposes.
  • Page 89 BIOS fw_usb1=off/on # BIOS Setup > Advanced > PCH-IO Configuration > USB Configuration > USB HS Physical Connector #1 /* Front Panel USB */ fw_usb2=off/on # BIOS Setup > Advanced > PCH-IO Configuration > USB Configuration > USB HS Physical Connector #2 /* backplane USB */ fw_usb3=off/on # BIOS Setup >...
  • Page 90 BIOS fw_cpu_hp=off/on # BIOS Setup > power > CPU Configuration > Hardware Prefetcher fw_cpu_acp=off/on # BIOS Setup > power > CPU Configuration > Adjacent Cache Line Prefetch fw_cpu_vt=off/on # BIOS Setup > power > CPU Configuration > Intel (VMX) Virtualization Technology fw_cpu_ht=off/on # BIOS Setup >...
  • Page 91 BIOS or one of the following predefined selfspeaking names efisdcard # EFI on board microSD sdcard # legacy option - on board SD card efiobsata # EFI On board SATA efiiomsata0 efiiomsata1 obsata # legacy option - on board SATA efishell efinet4 (MAC) # MAC - MAC address in the form XX-XX-XX-XX-XX-XX efinet6 (MAC) # MAC - MAC address in the form XX-XX-XX-XX-XX-XX...
  • Page 92 BIOS SharpStreamer™ Pro PCIE-7210 Installation and Use ( 6806800U29D)

  • Page 93: Base Operating System

    Chapter 6 Base Operating System The Base Operating System software contains open source CentOS Linux release 7.2.1511 (Core) distribution with kernel patches to support PCIE-7210 card. The kernel version of CentOS release is 3.10.0-327. Installing kernel is a one time installation and it would be the first time when you install it.

  • Page 94: Booting Options

    Base Operating System The following are the three methods for installing or booting this software on PCIE-7210: Installing and booting from CD/DVD.  Installing and booting from USB stick.  Booting diskless client through network (PXE booting).  Booting Options This section explains how to create various bootable sources and also steps required to install software on the disk from each of these bootable sources.

  • Page 95: Booting Via Usb Drive

    Base Operating System 6.2.2 Booting via USB drive 6.2.2.1 Creating a bootable USB on a Linux Machine Prerequisites 1 GB USB drive  A PC with CentOS7.2 with extlinux, syslinux, sgdisk, and parted installed.  The installation script will verify these utilities and abort, if not available. To create a bootable USB on Linux machine: 1.

  • Page 96: Booting Via Pxeboot

    Base Operating System 4. Select the following options in rufus. Option Selection Device Select the USB drive that you have inserted. Partition scheme and GPT partition scheme for UEFI target system type File System Fat32 Cluster Size 8192 bytes New Volume Label PCIE7210-BOOT Format options Quick format...
  • Page 97 Base Operating System Configuring the Host Server To boot the software through PXE, perform the following steps on the host server: 1. Copy the EFI images content on the ISO to the /tftpboot/7210 directory. $ mount PCIE7210-BOOT-ISO.iso /mnt $ mkdir –p /tftpboot/7210 $ cp –r /mnt/images /mnt/EFI /tftpboot/7210 2.
  • Page 98 Base Operating System server_args = -s /tftpboot disable = no per_source = 11 cps = 100 2 flags = IPv4 DHCPD Server Configuration Modify the DHCPD server configuration as shown in the sample dhcpd.conf file, generally available in /etc/dhcp location. # DHCP Server Configuration file.# see /usr/share/doc/dhcp*/dhcpd.conf.example # see dhcpd.conf(5) man page...

  • Page 99: Installation

    Base Operating System Boot the PCIE-7210 card 1. Press <ESC> key during BIOS booting. 2. Select Boot Manager and select the EFI network to Boot From. 3. Login as root/root. For more information on how to connect the console, refer to the section Linux Distribution on page 104.
  • Page 100 Base Operating System 5. Obtain the IP using dhclient or assign IP address manually to an interface, if the installation requires network access. 6. Use the following command to find out the exact disk. $/opt/bladeservices/tools/flashrfsrc.sh -s For connecting to iSCSI based disk, information is provided in subsequent sections. 7.

  • Page 101: Automatic Installation

    Base Operating System $ flashrfsrc.sh -d iscsi:iqn.2016-07.com.artesyn:initiator@eth0: 192.168.201.2:6000:iqn.2016-07.com.artesyn:target -i 192.168.201.2:/7210/release/images 6.2.4.1 Automatic Installation 6.2.4.1.1 Local Disk If the installation is onto a local disk with the following information. Disk: sda  Images Location: /media/usbdrive/images  Usage Command $ opt/bladeservices/tools/flashrfsrc.sh -d disk:sda -i local:/media/usbdrive/images 6.2.4.1.2 iSCSI disk If the installation is onto a iSCSI disk, with following information.

  • Page 102: Manual Installation

    Base Operating System Usage Command $ /opt/bladeservices/tools/flashrfsrc.sh -d iscsi:iqn.2016- 07.com.artesyn2: initiator@eth0:192.168.201.2:5000:iqn.2016- 07.com.artesyn2:target -i 192.168.201.2:/7210/images Disk selection in BIOS 1. Reboot the card, go to BIOS and perform the following steps: Select UEFI mode  Select the installed disk as the first bootable drive, for iSCSI based disk and go to ...
  • Page 103 Base Operating System 5. Customizing partitions: A default partitioning scheme is displayed, You can choose to modify, if required. All partition sizes are based on GB. 6. Provide the path of the installable files location. What is the installation files directory? [] /media/usbdrive/images If booted from USB drive, then installable files are available in the /images directory.

  • Page 104: Linux Distribution

    Base Operating System 6. Provide the path of the installable files location. What is the installation files directory? [] /media/usbdrive/images If booted from USB drive, then installable files are available in the /images directory. The script performs formatting, partitioning and installation. 7.

  • Page 105: Connecting The Console

    Base Operating System Connecting the Console 6.3.1 CPU1 and CPU2 serial consoles are exposed via faceplate through Silicon labs (CP2105) single- chip USB to Dual UART bridge. Connect a microUSB to USB cable with mircoUSB end to the CONSOLE on the faceplate and the other end to the PC or laptop. For Windows 7 or Later: Teraterm Drivers are automatically installed up to connecting the cable.

  • Page 106: Ethernet Interfaces

    Base Operating System 6.3.2 Ethernet Interfaces This section provides information on Ethernet device (s) interfaces. Backplane Ethernet devices assigned to aCPU have the following naming convention.  e_s<physical_slot_id>d<device_id>f<function> aCPU (onboard Ethernet devices) mCPU (all Ethernet devices) have the following naming ...
  • Page 107 Base Operating System Host machine OS: Same distribution as Base OS ISO.  For example, if Base OS is based on CentOS7.2, then use a host machine installed with CentOS7.2. Procedure To modify ramfs, perform the following steps: 1. Mount the Base OS ISO to a directory. For example, /mnt directory.
  • Page 108 Base Operating System SharpStreamer™ Pro PCIE-7210 Installation and Use ( 6806800U29D)

  • Page 109: Pcie Software

    Chapter 7 PCIE Software PCIE software contains necessary RPMs to make the SharpStreamer Pro 7210 card work as an mCPU or as an aCPU in a MaxCore environment. The software is closely tied to a particular Kernel software and Base OS distribution and related information that are available from the release notes.

  • Page 110: Installation

    PCIE Software Table 7-1 Package Information (continued) Package Name Description Creates a combined bootable ISO image with Base create_updated_iso.sh OS ISO and PCIEUpdate ISO. PCIe package removal script. pcie-update-erase.sh Installation This installation is applicable for both mCPU and aCPU. Prerequisite You need to upgrade Baseboard Firmware of the chassis.

  • Page 111: Pcie Update

    PCIE Software PCIE Update 7.2.2 Prerequisite You need to install MC3K_7210 _OS_CENTOS72_DIST_<Release and Version number>.iso and MC3K_7210_OS_CENTOS72_KERNEL_UPDATE_<Release and Version number>.iso on the card storage and boot from the installed image. Note: Check the release notes for the exact version information. The card should be running with the required OS.

  • Page 112: Firmware Upgrade

    PCIE Software gz: large size, fast creation, fast booting xz: small size, slow creation, slow booting The following bootable ISO image is generated. MC3K_7210 _OS_CENTOS72_DIST_<Release and Version number>_updated.iso Firmware Upgrade Applicable: For mCPU and aCPU Related packages: fcu and pcie-firmware pcie-firmware RPM located in /opt/bladeservices/rom location contains BIOS and CPLD firmware.
  • Page 113 PCIE Software The following screen shows a typical output when the above command is executed. The above screen depicts the following information. Device #00 represents the CPLD and the firmware version is 01.05.00.  Device #01 represents BIOS and the firmware version is 2.0.00000000. ...
  • Page 114 PCIE Software The following screen shows a typical output when the above command is executed. After completion of this procedure the image is copied to the flash temporary location. Once the upgrade procedure shows the result as Success (as notified in the above screen), the upgrade procedure would complete with the rebooting of the card.

  • Page 115: Cpld Upgrade

    PCIE Software Wait until the above procedure is successful. Do not reset or reboot the card at this point of time. This may corrupt the BIOS. Once the upgrade is successful, card will go for automatic reset and then boots with the upgraded BIOS.

  • Page 116: Boardcontrol

    PCIE Software Here, <CPLD image>.fri is the firmware file to which CPLD will be upgraded. For more information on where to find this file, contact your local Artesyn sales representative. The following screen shows a typical output when the above command is executed. For the newly upgraded CPLD image to be active, you need to PowerCycle the card After the card boots to Linux, to confirm whether the CPLD is upgraded, execute the fcu –q command.

  • Page 117: Fpga_Tool

    PCIE Software pcie7210_sensors utility is available in the /opt/services/bin directory and you can execute at command line to read the various sensor readings.This utility provides the readings of all sensors on a single execution. The following is sample code showing utility and its output. [root@pcie7210 ~]# ./pcie7210_sensors Core0: +69.0°C (high Core1: +76.0°C (high Core2: +62.0°C (high Core3: +66.0°C (high...

  • Page 118: Maxcore Pcie Management

    PCIE Software MaxCore PCIe Management This is applicable for mCPU and the related package is pciemgmt. The MaxCore ExpressFabric switch has the unique capability to connect each individual Virtual Function (VF) on single root I/O virtualization (SRIOV) capable PCIe cards to one of many CPUs. Many VFs can surely be connected to the same CPU and the CPU’s hypervisor can connect VFs to Virtual Machines (VMs).

  • Page 119: Mccs Service Startup Details

    PCIE Software The following steps are executed when the BMC is ready and you have pressed the power button: 1. The BMC turns on the 12V payload (main) power and switches the power button LED to permanently ON. 2. Power is provided to all PCIe slots and onboard devices. Any PCIe I/O (downstream) card will power-up now and an Artesyn host card (PCIE-7410) will be ready to be powered-up.

  • Page 120: Maxcore Configuration Service (Mccs)

    PCIE Software If a PCIE-7410 is replaced by any PCIe I/O card or vice versa  If you manually configure any slot that differs from the previous auto detected one  Any PCIE-7410 Application CPU is powered on by the MCCS service at Management CPU startup.

  • Page 121: Figure 7-1 Software Architecture

    PCIE Software To communicate with the MaxCore Configuration Service (MCCS), a configuration client API (written in Python) is provided. Both communicate through the Advanced Message Queue Protocol (AMQP). This requires that an AMQP Server runs on the mCPU which is the RabbitMQ implementation.

  • Page 122: Mccs Deployment

    PCIE Software Get and Set the chassis number  Get and Set the PEX mode  List and Set SATA disk assignments to CPUs  7.6.2.1 MCCS Deployment The configuration service is part of pciemgmt package. Only the pciemgmt together with the RabbitMQ are started by the system on the mCPU.

  • Page 123: List Cpus

    PCIE Software You can get the list of functions for each slot and device. With the location string, you can find the PCI address of the functions at the management CPU in format <bus:slot.function>. You can use the lscpi command to get more information about all PCI buses and devices. 7.6.2.4 List CPUs To list CPUs and their root ports, use the following command.

  • Page 124: Remove A Device Function From A Cpu

    PCIE Software 7.6.2.6 Remove a device function from a CPU You can remove a device function from a CPU with the remove-func method. For this, you have to specify the address information of the CPU and of the device function as shown below. mccs_tool.py --method=remove-func --cpu=<slot,cpu,root-port>...

  • Page 125: Get The Assigned Cpu Of A Device Function

    PCIE Software 7.6.2.9 Get the assigned CPU of a device function If you want to know if there is already a CPU assigned to a device function you can use the method get-assigned-cpu. You have provide the address information of the device function as shown below.

  • Page 126: 7.6.2.13 Get And Set The Power State Of A Cpu

    PCIE Software 7.6.2.13 Get and Set the Power state of a CPU To know whether a CPU in the chassis is powered on or powered off, use mccs_tool.py – method=get-cpu-ower –cpu=<slot,cpu num> To power down a CPU, use the command mccs_tool.py –method=set-cpu-power – power=down To reset a CPU, use the command mccs_tool.py –method=set-cpu-power –...

  • Page 127: Mccs Config File At Bmc

    PCIE Software 7.6.2.16.1 MaxCore Configuration service is not running 1. Check the status of the MCCS. systemctl status pciemgmt.service 2. If MCCS is not active, check the status of the RabbitMQ. systemctl status rabbitmq-server.service 3. If the RabbitMq is active, restart MCCS. systemctl start pciemgmt.service 7.6.2.16.2 RabbitMQ is not running 1.

  • Page 128: Shutdown Behavior For Mcpu

    PCIE Software MCCS tool also provides the following two methods to handle the config file at the BMC side. Table 7-2 ETH3 and ETH4 IP Address Assignment Method Description Reads the mccs configuration file that is stored on the BMC. get-bmc-config Removes the mccs configuration file on the BMC remove-bmc-...

  • Page 129: Network Interfaces

    PCIE Software Network Interfaces Applicable: mCPU and aCPU Related package: pcie-mcpu-basetnet 7.7.1 Backplane Interfaces 7.7.1.1 Onboard Niantic MaxCore has an on-board dual-port 10G Niantic device, which is used for default networking connectivity. Each port can share up to 40 VFs for device assignment to aCPUs. This device is located in Slot 16, which is not accessible to user directly.

  • Page 130: Acpu

    PCIE Software The following IP addresses are assigned by default to ETH3 and ETH4 interfaces. Table 7-3 ETH3 and ETH4 IP Address Assignment Interface IP Address ETH3 172.27.<chassis_id>.2 ETH4 172.26.<chassis_id>.2 pcie-mcpu-basenet service generates the related ‘ifcfg-‘ scripts. These are generated on every boot.

  • Page 131: Maxcore Firmware Upgrade

    Appendix A MaxCore Firmware Upgrade MaxCore Firmware Upgrade There are several firmware elements in a MaxCore system that may need upgrades throughout the product’s life cycle. Some firmware elements are part of the system itself and some reside on PCIe cards. This section provides information on how to upgrade the firmware elements that are part of the system only.

  • Page 132: Upgrade Procedure

    MaxCore Firmware Upgrade You can manage the system firmware elements as HPM.1 components. You can determine the revision of the HPM.1 firmware components using the tool called ipmitool. You can download it from http://ipmitool.sourceforge.net. There are different versions of ipmitool available, each using different command sets to the BMC.
  • Page 133 MaxCore Firmware Upgrade You can upgrade the BMC firmware through the BMC’s web browser accessed from the remote machine (network connection from remote machine to BMC required) through the IP address 192.168.201.9 with Username admin and Password admin Firmware upgrades via web browser are only supported by firmware revisions higher than v1.0.10 (the BMC firmware revision can be retrieved with ipmitool, refer to Obtaining Revisions of Firmware Components on page 131).

  • Page 134: Figure A-1 Dual Image Configuration

    MaxCore Firmware Upgrade To view more details, open the Dual Image Configuration screen by clicking Firmware Update > Dual Image Configuration. Figure A-1 Dual Image Configuration In the Dual Image Configuration screen, choose the required Image (that need to be booted after firmware option upgrade) and click Save. SharpStreamer™...

  • Page 135: Figure A-2 Firmware Update - Upgrade

    MaxCore Firmware Upgrade To open Firmware Update screen, click Firmware Update > Firmware Update from menu bar. Figure A-2 Firmware Update - Upgrade Do not modify the image to be updated. Never update the image you have booted successfully from. SharpStreamer™...
  • Page 136 MaxCore Firmware Upgrade Select Preserve Configuration to preserve the network configuration (IP,  username, password, DHCP, VLAN). Click Enter Update Mode and follow the wizard through the upgrade. Select  Full Flash check box to perform a complete firmware upgrade always. 2.
  • Page 137 MaxCore Firmware Upgrade ./ipmitool –I lan –H 192.168.201.9 –U admin –P admin hpm upgrade mc3000-cpld-glue-0.3.0.hpm component 2 force If you observe that the firmware upgrade fails, repeat the firmware upgrade  procedure again Firmware upgrade progress is not seen immediately. As the first step, the ipmitool ...

  • Page 138: Troubleshooting

    MaxCore Firmware Upgrade In any case, if you observe that the firmware upgrade fails, repeat the firmware  upgrade procedure again You cannot see the Firmware upgrade progress immediately. As the first step, the  ipmitool loads the firmware image into the BMC. This may take some time (~2min).

  • Page 139: Bmc Fw Upgrade Failed

    MaxCore Firmware Upgrade In case when ipmitool reports “Firmware upgrade procedure failed” message, power cycle the system, and evaluate the firmware revision of the firmware component just programmed (for more details refer to Obtaining Revisions of Firmware Components on page 131, and if the revision programmed is not performed before, repeat the firmware upgrade procedure.
  • Page 140 MaxCore Firmware Upgrade SharpStreamer™ Pro PCIE-7210 Installation and Use ( 6806800U29D)

  • Page 141: Related Documentation

    3. In the Search text box, type product or manual name and click Filter. Table B-1 Artesyn Embedded Technologies - Embedded Computing Publications Document Title Publication Number SharpStreamer Pro PCIE-7210 Quick Start Guide 6806800U27 SharpStreamer Pro PCIE-7210 Safety Notes Summary 6806800U28...
  • Page 142 Related Documentation SharpStreamer™ Pro PCIE-7210 Installation and Use ( 6806800U29D)
  • Page 144 Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc. All other product or service names are the property of their respective owners. © 2017 Artesyn Embedded Technologies, Inc.

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