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5
D
DDP2P5V
L4
120 OHM
C17
0.1U Z
C
P3P3V
L5
VDDMOSC
120 OHM
MOSCEN
R11
10K
C19
C20
0.1U Z
0.1U Z
Pixel Clock (74.25MHz) from Scalar
SERIES CONTROL PORT 0
SCPDO
(To MUSTANG)
SCPDI
SCPCLK
DDP3P3V
B
R13
R14
1.33KF
1.33KF
SW1
6240019001
A
5
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P5V
R7
R8
10K
10K
IIC Bus (open drain)
SDA_D
SCL_D
Minimize Noise on PLL_VCCA
C18
0.1U Z
OCLKA
Master Clock (100MHz)
4
3
VCC
OUT
C31
R10
1
2
OE
GND
22P J
39.2F
Y1
100MHZ
L19
220OHM
68.00129.0D1
CLKIN
DDP3P3V
R12
DRCGPDZ
1K
DADSELZ
MTRPWM
DMDSPARE0
DMDSPARE1
DMDSPARE0
DMDSPARE1
MTRRSTZ
(To SSI Motor)
MTRSELZ
MTRCLK
DDP3P3V
MTRDATA
TP2
TP1
DADINTZ
R114
R115
R113
10K
10K
10K
DIO24
IDO25
CWINDEX
MTRDMUX
DMDRSTZ
DMDSELZ
DIO31
R116
NC_R0603
4
FLDATA[0..15]
FLDATA0
AG26
FLDATA0
FLDATA1
AH26
FLDATA1
FLDATA2
AJ26
FLDATA2
FLDATA3
AF25
FLDATA3
FLDATA4
AG25
FLDATA4
FLDATA5
AJ25
FLDATA5
FLDATA6
AJ24
FLDATA6
FLDATA7
AF24
FLDATA7
FLDATA8
AG24
FLDATA8
FLDATA9
AH24
FLDATA9
FLDATA10
AF23
FLDATA10
FLDATA11
AG23
FLDATA11
FLDATA12
AG22
FLDATA12
FLDATA13
AJ22
FLDATA13
FLDATA14
AF20
FLDATA14
FLDATA15
AJ21
FLDATA15
AH23
SDA0
AF22
SCL0
AG28
APLLMD1
AF28
APLLMD0
AG29
PLL_VCCA
AF27
COSC
F3
MOSCN
MOSC
F2
MOSC
MCRYSTALEN
G4
MCRYSTALEN
G3
POSCN
G2
POSC
H4
PCRYSTALEN
T26
WCLK
TP30
TP29
TP28
AB28
DIO0
AA26
DIO1
AB27
DIO2
AB26
DIO3
AC28
DIO4
AC27
DIO5
AC26
DIO6
TP31
PWM0
AD28
DIO7
TP32
PWM1
AD27
DIO8
AD29
DIO9
AE28
DIO10
AE29
DIO11/ASICID0
AE27
DIO12/ASICID1
AE26
DIO13/ASICID2
AF29
DIO14
AH3
DIO15
AG4
DIO16
AH4
DIO17
AJ4
DIO18
AF5
DIO19
AG5
DIO20
ARMTEST1
AH6
DIO21
ARMTEST2
AF7
DIO22
AG7
DIO23
TP33
TP27
TP26
AB3
DIO24
AB4
DIO25
AC2
DIO26
AC3
DIO27
AC4
DIO28
AD2
DIO29
AD3
DIO30
AD4
DIO31
U2B
Micro, Clocks ,SR16 and Flash interface
4
3
DDP1010
AH7
FLADDR19
FLADDR18
AF8
FLADDR18
FLADDR17
AG8
FLADDR17
FLADDR16
AF9
FLADDR16
FLADDR15
AG9
FLADDR15
FLADDR14
AH9
FLADDR14
FLADDR13
AG10
FLADDR13
FLADDR12
AJ10
FLADDR12
FLADDR11
AG13
FLADDR11
FLADDR10
AH13
FLADDR10
FLADDR9
AJ14
FLADDR09
FLADDR8
AF15
FLADDR08
FLADDR7
AJ15
FLADDR07
FLADDR6
AJ17
FLADDR06
FLADDR5
AH17
FLADDR05
FLADDR4
AH18
FLADDR04
FLADDR3
AG19
FLADDR03
FLADDR2
AH20
FLADDR02
FLADDR1
AJ20
FLADDR01
FLADDR0
AG20
FLADDR0
AH27
FL_OE
AJ27
FL_WE
AF19
FL_CS
TP39
TP40
V2
SR16STRB
W3
SR16OEZ
R4
SR16ADDR3
R1
SR16ADDR2
U1
SR16ADDR1
U2
SR16ADDR0
N2
SR16MODE1
P1
SR16MODE0
Y2
SR16SEL1
Y1
SR16SEL0
J3
DMDBIN3
K3
DMDBIN2
K1
DMDBIN1
N3
DMDBIN0
TP37
AB1
SR16VCCEN
Y4
DMDVCCEN
AA1
VCC2EN
Y3
VBIASEN
W4
VRSTEN
AF1
SCP1_CLK
AF2
SCP1_DO
AF3
SCP1_DI
TSTPNT3
A21
TSTPNT3
TSTPNT2
D19
TSTPNT2
TSTPNT1
C20
TSTPNT1
TSTPNT0
A20
TSTPNT0
J2
OCLKF
H3
OCLKE
F1
OCLKD
E1
OCLKC
D1
OCLKB
OCLKA1
E3
OCLKA
C1
PUM_ARSTZ
D2
EXT_ARSTZ
D3
EXT_ARST
DDP1010
TP34
3
2
P3P3V
FLADDR[0..18]
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FLAD
FL_OEZ
FL_WEZ
FL_CSZ
TP41
SR16STROBE
(To DAD1000)
SR16OEZ
SR16ADDR3
SR16ADDR2
SR16ADDR1
SR16ADDR0
SR16MODE1
SR16MODE0
SR16SEL1
SR16SEL0
TP38
SERIES CONTROL PORT 1
(To DAD1000)
SCP_CLK
SCP_DO
SCP_DI
TP45
TP46
TP47
TP48
(v-sync, delay CWI, spoketest for debug
TP36
50MHz Clock
R15
22
OCLKA
PUM_ARSTZ
(To DAD1000)
EXT_ARSTZ
TP35
2
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