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5
CPU_D[0..7]
CPU_D[0..7]
D
CP U_D0
CP U_D1
CP U_D2
CP U_D3
CP U_D4
CP U_D5
CP U_D6
CP U_D7
CPU_A[0..7]
CPU_A0
CPU_A1
CPU_A2
CPU_A3
CPU_A4
CPU_A5
CPU_A6
CPU_A7
C
CPU_RXD0
CPU_TXD0
B
A
The RM1_WR_N is
delayed by 2 gates
because the data
should be stable
RM1_WR_N
during the falling
edge of the WRITE
signal.
5
All manuals and user guides at all-guides.com
RESET_N
RESET_N
SDA
SDA
SCL
SCL
R122 0
FAN_CTRL
R123 0
DMD_SCL
DMD_SDA
CPU_PCS0_N
CPU_PCS0_N
Note: Instead of KM616V1000B,
IS61LV25616-12T (256K x 16 bit
4M) can be stuffed for debug.
CPU_A5
1
A4
CPU_A4
2
A3
CPU_A3
3
A2
CPU_A2
IS61LV25616-12T
4
A1
CPU_A1
5
A0
CPU_LCS_N
6
CS#
CP U_D0
7
I/O1
CP U_D1
8
I/O2
CP U_D2
9
I/O3
CP U_D3
10
I/O4
11
+3VS
VCC
12
VSS
CP U_D4
13
I/O5
CP U_D5
14
I/O6
CP U_D6
15
I/O7
CP U_D7
16
I/O8
CPU_WR_N
17
WE#
CPU_A16
18
A15
CPU_A15
19
A14
CPU_A14
20
A13
CPU_A13
21
A12
CPU_A17
22
NC
(128KBytes SRAM)
CPU_A17
CPU_A16
1
A15
CPU_A15
2
A14
CPU_A14
3
A13
CPU_A13
4
A12
CPU_A12
5
A11
CPU_A11
6
A10
CPU_A10
7
A9
CPU_A9
8
A8
10K
HI_A19
9
+3VS
A19
R65
10
NC
CPU_WR_N
11
WE#
12
RESET#
13
NC
14
NC
15
RY/BY#
CPU_A19
16
A18
CPU_A18
17
A17
CPU_A8
AM29LV160DT-90EI
18
A7
CPU_A7
19
A6
CPU_A6
20
A5
CPU_A5
21
A4
CPU_A4
22
A3
CPU_A3
23
A2
CPU_A2
24
A1
(256K x 16Bit FLASH)
+3VS
CPU_A1
R69
10K
CPU_WR_N
CPU_WR_N
CPU_RD_N
CPU_RD_N
ANTI_CLKDIV
MUX_BUFFER
MUX_BUFFER
(PIO20)
MUX_SEL_P
MUX_SEL_P
RM1CLKIN
+3VS
U7B
4
R74
33
CPU_DELAY2
CPU_DELAY1
6
5
74VHC32
4
+3VS
R114
R115
5.1K
5.1K
CPU_A6
44
A5
CPU_A7
43
A6
U9
CPU_A8
42
A7
CPU_RD_N
41
OE#
CPU_BHE_N
40
UB#
CPU_A0
39
LB#
CPU_D15
38
I/O16
CPU_D14
CP U_D0
37
I/O15
CPU_D13
CP U_D8
36
I/O14
CPU_D12
CP U_D1
35
I/O13
CP U_D9
34
VSS
CP U_D2
33
+3VS
VCC
CPU_D11
CPU_D10
32
I/O12
CPU_D10
CP U_D3
31
I/O11
CP U_D9
CPU_D11
30
I/O10
CP U_D8
CP U_D4
29
I/O9
CPU_D12
28
NC
CPU_A9
CP U_D5
27
A8
CPU_A10
26
A9
CPU_A11
CPU_D13
25
A10
CPU_A12
CP U_D6
24
A11
CPU_A18
23
NC
CPU_D14
CP U_D7
CPU_D15
E1
CPU_TXD1
CPU_RXD1
CPU_RXD0
CPU_TXD0
+3VS
48
A16
47
BYTE#
46
VSS
CPU_D15
45
DQ15/A-1
CP U_D7
44
DQ7
CPU_D14
43
DQ14
CP U_D6
42
DQ6
CPU_D13
41
DQ13
CP U_D5
40
DQ5
CPU_D12
39
DQ12
CP U_D4
38
DQ4
37
VCC
CPU_D11
36
DQ11
CP U_D3
35
DQ3
CPU_D10
34
DQ10
U12
CP U_D2
33
DQ2
CP U_D9
32
DQ9
CP U_D1
31
DQ1
CP U_D8
30
DQ8
CP U_D0
29
DQ0
CPU_RD_N
28
OE#
27
VSS
26
CE#
25
A0
R68
FLASH1_CE
CPU_UCS_N
NC_R0603
(PIO29)
R71
33
R72
33
(PIO21)
TP45
+3VS
U7C
9
CPU_WR_N
8
10
74VHC32
4
3
+3VS
R47
R48
10K
10K
+3VS
78
AD0
79
AD8
80
AD1
81
AD9
82
AD2
83
AD10
84
AD3
85
AD11
86
AD4
87
AD12
88
AD5
89
GND
U10
90
AD13
RDC8820
91
AD6
92
VCC
93
AD14
94
AD7
95
AD15
TP42
96
S6/LOCK/CLKDIV2
CPU_UZI
1
97
UZI
98
TXD1
99
RXD1
100
CTS0/ENRX0
1
RXD0
2
TXD0
+3VS
R63
10K
C PU_ARDY
E1
TP43
R70
33
R73
33
Note: Infra-Red generates two interrupts: at the rising edge and at
for IR signal decoding.
C77
+
22UF/16
C78
C79
C80
0.1UF
0.1UF
0.1UF
3
2
U6
1
8
NC
VCC
2
7
NC
WP
3
6
NC
SCL
4
5
GND
SDA
AT24C16
PIO1
R38
33
SDA
SCL
+3VS
R39
R40
R41
R42
10K
10K
10K
10K
R43
NC_R0603
PIO17_1
R49
PIO19
U8A
(INT1)
INT0
3
(PIO2)
INT2
+3VS
R54
NC_R0603
INT4
52
INT4
CPU_MCS1_N
51
MCS1
RM1_CS_N
50
MCS0
PIO5
49
DEN/DS
PIO4
48
DT/R
CPU_NMI
R61 0
47
NMI
46
SRDY
CP U_HOLD
45
HOLD
CPU_HLDA
44
HLDA
CPU_WLB
43
WLB
CP U_WHB
42
WHB
41
GND
CPU_A0
40
A0
CPU_A1
39
A1
38
VCC
CPU_A2
37
A2
CPU_A3
36
A3
CPU_A4
35
A4
CPU_A5
34
A5
CPU_A6
33
A6
CPU_A7
32
A7
CPU_A8
31
A8
CPU_A9
30
A9
CPU_A10
29
A10
CPU_A11
28
A11
CPU_A12
CPU_A13
CPU_A14
CPU_A15
CPU_A16
CPU_A17
E1
CPU_A18
CPU_A19
TP44
R67
1M
X2
25MHZ
3
1
C75
C76
20PF
20PF
L6
Z1000/100MHZ
C81
C82
C83
C84
C85
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
2
R35
5.1
33
+3VS
74H
R62 1K
RESE
C86
0.1
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