Self-Checking And Functional Test - ABB MDAR Instruction Manual

Section 8. SELF-CHECKING AND FUNCTIONAL TEST
8.1 SELF-CHECKING
Self-testing is a major benefit of microprocessor-
based relays. At all times, MDAR (REL-300) monitors
its ac input subsystems using multiple A/D converter
calibration check inputs, plus loss-of-potential and
loss-of-current monitoring (as described in Chapter
IX). Failures of the converter, or any problem in a sin-
gle ac channel which unbalances nonfault inputs, are
alarmed. The self-checking covers the following
areas:
(a) Analog Front End Test
One of the inputs to the analog multiplexer is a
test input. This input voltage can be switched
between +2.5 V and -0.3 V for input to the A/D
converter. Periodic testing of these voltages
tests the analog front end for proper operation.
In this way the multiplexer, sample/hold, rang-
ing circuitry, and A/D converter are tested.
(b) Program Memory Checksum
Immediately upon power-up the relay executes
a complete ROM checksum of program mem-
ory. During operation, the MDAR (REL-300)
relay continually computes and verifies the pro-
gram memory checksum.
(c) Power-up RAM Test
Immediately upon power-up the relay does a
complete test of the RAM data memory.
(d) Nonvolatile RAM Test
All settings for the system operation are stored
in non-volatile RAM in three identical arrays.
These arrays are continuously checked by the
program. If all three array entrees disagree with
each other, a non-volatile RAM failure is
detected.
(e) Processor Tests
Several tests are included to verify the opera-
tion of the microprocessor. On power-up, the
processor I/O status registers are checked
while they are still in a known state. Other tests
performed both at power-up and during normal
operation are listed below:
• Tests processor flags, stack, and timer.
• Tests program counter, execution time, and RAM.
• Tests addition and subtraction.
For failures which do not disable the processor,
MDAR (REL-300) jumps to the TEST mode status
display (STAT) to show the cause of the problem. The
cause of the problem is represented by their corre-
sponding bits (zero thru 6) in the value field.
Bit 0 External RAM Failure
Bit 1 EEPROM warning
Bit 2 ROM (EPROM) checksum error
Bit 3 EEPROM Failure (Non-Volatile memory)
Bit 4 Analog Input Circuit Failure
Bit 5 Processor Failure
Bit 6 Wrong setting on JMP2 for single-pole trip
or programmable output contact
selections.
All bits are expressed in a HEX byte form. For exam-
ple: If the display shows "STAT 1B", whose binary
representation is 0001 1011, the relay failed the self-
test in the area of External RAM (bit 0), EEPROM
(one-out-of-three failure, bit 1), EEPROM (two-out-of-
three failure, bit 3) and Analog Input Circuit (bit 4).
Normally, the test mode should show "STAT 0". This
means that the relay passes the self-test routines.
Bit 6 is for the setting discrepancy detection. For
example, if the order information calls for single-pole
trip option and the jumper #2 on the processor mod-
ule is on position "1-2" which is for 3-pole trip, the
MDAR (REL-300) will give the error of "TEST 40".
8.2 LOP AND LOI CONDITIONS
MDAR (REL-300) contains loss-of-potential (LOP)
and loss-of-current (LOI) logic which monitors the
analog inputs. The loss of a voltage or current input
which is not caused by a fault condition enables the
GS alarm relay. In addition, tripping is disabled dur-
ing a LOI condition if the LOIB setting is set to YES.
However, only the distance measurement units are
disabled during a LOP condition if the LOPB setting
is set to YES. The LOP and LOI status displays are
included in the monitored data.
8.3 OUTPUT CONTACT TESTS
The output contact test, a "Push-to-close" approach,
is included in MDAR (REL-300) for checking all out-
put relay contacts. It is designed for a bench test only.
The test is for used to verify the operation of the con-
I.L. 40-385.5
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