Introduction To Synthesizer Troubleshooting - Nokia RM-51 Service Manual

RM-51
Nokia Customer Care RF troubleshooting

Introduction to synthesizer troubleshooting

Figure 153 Synthesizer block diagram
The VCO frequency is locked by a PLL (phase locked loop) into a stable frequency source given by a VCTCXO, which
is running at 26 MHz. The frequency of the VCTCXO is in turn locked into the frequency of the base station with
the help of an AFC (automatic frequency control) voltage, which is generated in UEMEK by an 11-bit D/A (digital-
to-analog) converter.
The PLL is capable of tuning frequency range for GSM bands 900/1800/1900. It is integrated in Helgo and
controlled through the RFBus. The PLL consists of a 64/65 (P/P+1) prescaler, N- and A-divider, reference divider,
phase detector and a charge pump for the external loop filter.
The 4 GHz oscillator signal, generated by the VCO, is fed through a 180 degrees balanced phase shifter to the
prescaler and the output of the prescaler is fed to the N- and A-divider, which produces the input to the phase
detector. The phase detector compares this signal to the reference signal, which is divided by the reference
divider from the VCTCXO frequency.
The frequency of the reference signal is 400 kHz. The output of the phase detector is connected to the charge
pump, which charges or discharges the integrator capacitor in the loop filter depending on the phase of the
measured frequency compared to the reference frequency.
The integrator output voltage is finally connected to the control input of the VCO. The VCO operates at the
channel frequency multiplied by two in GSM1800/1900 and by four in EGSM900.
The required frequency dividers for modulator and demodulator mixers are integrated in Helgo.
The loop filter filters out the comparison pulses of the phase detector and generates a DC control voltage to the
VCO. The loop filter determines the step response of the PLL (settling time) and contributes to the stability of
the loop.
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