Uart Interface - Quectel LTE Standard Module Series Hardware Design

A common mode choke L1 is recommended to be added in series between the module and customer's
MCU in order to suppress EMI spurious transmission. Meanwhile, the 0Ω resistors (R3 and R4) should be
added in series between the module and the test points so as to facilitate debugging, and the resistors are
not mounted by default. In order to ensure the integrity of USB data line signal, L1/R3/R4 components
must be placed close to the module, and also these resistors should be placed close to each other. The
extra stubs of trace must be as short as possible.
The following principles should be complied with when design the USB interface, so as to meet USB 2.0
specification.

It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90Ω.

Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
important to route the USB differential traces in inner layer with ground shielding on not only upper
and lower layers but also right and left sides.

Pay attention to the influence of junction capacitance of ESD protection components on USB data
lines. Typically, the capacitance value should be less than 2pF.

Keep the ESD protection components to the USB connector as close as possible.

3.6. UART Interface

EG21-G Mini PCIe provides one main UART interface. The main UART interface supports 9600bps,
19200bps, 38400bps, 57600bps, 115200bps and 230400bps baud rates, and the default is 115200bps.
This interface supports RTS and CTS hardware flow control, and be used for AT command
communication and data transmission. The following table shows the pin definition of the interface.
Table 9: Pin Definition of Main UART Interface
Pin Name
UART_RX
UART_TX
UART_CTS
UART_RTS
The signal level of main UART interface is 3.3V. When connecting to the peripheral MCU/RAM,
customers need to pay attention to the signal direction. The reference circuit is as follows:
EG21-G_Mini_PCIe_Hardware_Design
Pin No. I/O
11 DI
13 DO
23 DI
25 DO
LTE Standard Module Series
EG21-G Mini PCIe Hardware Design
Power Domain
3.3V
3.3V
3.3V
3.3V
Description
UART receive data
UART transmit data
UART clear to send
UART request to send
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