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Parameter
Minimum time between falling edge
of Select line and first rising edge of
tSSetup
SPI clock.
Delay in Slave asserting TX line after
falling edge of SPI clock, or the first
tTxdDelay
bit after falling edge of the Select
line.
Time before rising edge of SPI clock
by which received data must be
tRxdSetup
ready
Time for which received data must
be stable after rising edge of SPI
tRxdHold
clock
Time for which the Select line will
be held after the sampling edge for
tSSHold
the final bit to be transferred
3.2.3.
Host Wake-Up Signal Handling
We name the pin number 23 of WizFi210 as "Host wake-up signal". Host wake-up signal is
ACTIVE HIGH signal. Host processor must give the SPI clock and SPI read operation, as long
as host wake-up signal is HIGH.
Whenever WizFi210 wants to transfer the data it asserts (HIGH) host wake-up signal. Once all
the data transferred from WizFi210 it again de-asserts (LOW) the signal.
Host processor will detect the host wake-up signal transition (LOW to HIGH) as edge triggered
interrupt and process the incoming data.
3.2.4.
SPI data handling
WizFi210 provides seven special control characters like SPI_XON(0xFD), SPI_XOFF(0xFA),
Control_ESCAPE(0xFB), SPI_IDLE(0xF5), SPI_LINK_READY(0xF3), SPI_LINK_FAIL_1(0x00)
and SPI_LINK_FAIL_2(0xFF) for informing WizFi210's communication status in SPI mode.
So, to distinguish between SPI control characters and user data, the SPI data transfer layer of
WizFi210 makes use of an octet (or byte) stuffing procedure about user data. When sending or
receiving SPI control characters, WizFi210 and host processor send those characters itself
without byte stuffing to a peer device. But when sending user data having the same character to
SPI control characters, WizFi210 and host processor should do byte stuffing in order to
distinguish it with SPI control characters.
WizFi210
Programmers' Guide
Description
Table 18 Timing information of SPI interface
(WIZnet Co., Ltd.)
Minimum
Maximum
4 core SPI
clock
periods +
68 ns
4 core SPI
clock
periods +
68 ns
15
3 core SPI
clock
periods +
14 ns
3 core SPI
clock
periods +
14 ns
Unit
mixed
mixed
ns
mixed
mixed
3-38
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